JAJSFI3A May 2018 – November 2018 TAS3251
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | GNCP | Reserved | GOSR | ||||
R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | R/W | 0 | Reserved |
6-4 | GNCP | R/W | 0 | GPIO Source for NCP clk – These bits select the SDOUT pin as clock input source when GPIO is selected as CP clock divider source
000: N/A
|
3 | Reserved | R/W | 0 | Reserved |
2-0 | GOSR | R/W | 0 | GPIO Source for OSR clk – These bits select the SDOUT pin as clock input source when GPIO is selected as OSR clock divider source.
000: N/A
|