The device has a bidirectional serial control interface that is compatible with the Inter IC (I²C) bus protocol and supports 400-kbps data transfer rates for random and sequential write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The master device uses the I²C control interface to program the registers of the device and to read device status.

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data transfer on the bus is serial, one bit at a time. The transfer of address and data is in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is HIGH to indicate start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. Figure 7-4 shows these conditions. The master generates the 7-bit slave address and the read/write (R/ W) bit to open communication with another device and then waits for an acknowledge condition. The device holds SDA LOW during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. The address for each device is a unique 7-bit slave address plus a R/ W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. The SDA and SCL signals require the use of an external pullup resistor to set the HIGH level for the bus. There is no limit on the number of bytes that the communicating devices can transmit between start and stop conditions. After transfer of the last word, the master generates a stop condition to release the bus.

Figure 7-4 Typical I²C Sequence

To communicate with the device, the I²C master uses addresses shown in Figure 7-4. Transmission of read and write data can be by single-byte or multiple-byte data transfers.