JAJSFT0B November   2017  – November 2019 TAS5720A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital I/O Pins
    6. 7.6  Master Clock
    7. 7.7  Serial Audio Port
    8. 7.8  Protection Circuitry
    9. 7.9  Speaker Amplifier in All Modes
    10. 7.10 Speaker Amplifier in All Modes
    11. 7.11 I²C Control Port
    12. 7.12 Typical Idle, Mute, Shutdown, Operational Power Consumption
    13. 7.13 Typical Characteristics (Mono Mode): fSPK_AMP = 384 kHz
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
      1. 9.2.1 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Speaker Amplifier Audio Signal Path
        1. 9.3.2.1 Serial Audio Port (SAP)
          1. 9.3.2.1.1 I²S Timing
          2. 9.3.2.1.2 Left-Justified
          3. 9.3.2.1.3 Right-Justified
        2. 9.3.2.2 DC Blocking Filter
        3. 9.3.2.3 Digital Boost and Volume Control
        4. 9.3.2.4 Digital Clipper
        5. 9.3.2.5 Closed-Loop Class-D Amplifier
      3. 9.3.3 Speaker Amplifier Protection Suite
        1. 9.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 9.3.3.2 DC Detect Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hardware Control Mode
        1. 9.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 9.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 9.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 9.4.1.5 Hardware Control Mode Select (HW/SCL Pin)
        6. 9.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 9.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 9.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 9.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 9.4.2 Software Control Mode
        1. 9.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.2.2 Serial Audio Port Controls
          1. 9.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 9.4.2.3 Channel Select via Software Control
        4. 9.4.2.4 Speaker Amplifier Gain Structure
          1. 9.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
        5. 9.4.2.5 I²C Software Control Port
          1. 9.4.2.5.1 Setting the I²C Device Address
          2. 9.4.2.5.2 General Operation of the I²C Control Port
          3. 9.4.2.5.3 Writing to the I²C Control Port
          4. 9.4.2.5.4 Reading from the I²C Control Port
    5. 9.5 Register Maps
      1. 9.5.1 Control Port Registers - Quick Reference
      2. 9.5.2 Control Port Registers - Detailed Description
        1. 9.5.2.1  Device Identification Register (0x00)
          1. Table 9. Device Identification Register Field Descriptions
        2. 9.5.2.2  Power Control Register (0x01)
          1. Table 10. Power Control Register Field Descriptions
        3. 9.5.2.3  Digital Control Register (0x02)
          1. Table 11. Digital Control Register Field Descriptions
        4. 9.5.2.4  Volume Control Configuration Register (0x03)
          1. Table 12. Volume Control Configuration Register Field Descriptions
        5. 9.5.2.5  Left Channel Volume Control Register (0x04)
          1. Table 13. Left Channel Volume Control Register Field Descriptions
        6. 9.5.2.6  Right Channel Volume Control Register (0x05)
          1. Table 14. Right Channel Volume Control Register Field Descriptions
        7. 9.5.2.7  Analog Control Register (0x06)
          1. Table 15. Analog Control Register Field Descriptions
        8. 9.5.2.8  Reserved Register (0x07)
        9. 9.5.2.9  Fault Configuration and Error Status Register (0x08)
          1. Table 16. Fault Configuration and Error Status Register Field Descriptions
        10. 9.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 9.5.2.11 Digital Clipper Control 2 Register (0x10)
          1. Table 17. Digital Clipper Control 2 Register Field Descriptions
        12. 9.5.2.12 Digital Clipper Control 1 Register (0x11)
          1. Table 18. Digital Clipper Control 1 Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Mono Output Using Software Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Startup Procedures- Software Control Mode
          2. 10.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.1.2.3 Component Selection and Hardware Connections
            1. 10.2.1.2.3.1 I²C Pull-Up Resistors
            2. 10.2.1.2.3.2 Digital I/O Connectivity
      2. 10.2.2 Mono Output Using Hardware Control
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.2.2.3 Digital I/O Connectivity
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 DVDD Supply
    2. 11.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB Footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 サポート・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.4.2.5.2 General Operation of the I²C Control Port

The TAS5720A-Q1 device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a START condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is HIGH to indicate START and STOP conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 11. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5720A-Q1 holds SDA LOW during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus.

TAS5720A-Q1 t0035-01.gifFigure 11. Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between START and STOP conditions. When the last word transfers, the master generates a STOP condition to release the bus. A generic data transfer sequence is shown in Figure 11.