JAJSFT0B
November 2017 – November 2019
TAS5720A-Q1
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
機能ブロック図
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Digital I/O Pins
7.6
Master Clock
7.7
Serial Audio Port
7.8
Protection Circuitry
7.9
Speaker Amplifier in All Modes
7.10
Speaker Amplifier in All Modes
7.11
I²C Control Port
7.12
Typical Idle, Mute, Shutdown, Operational Power Consumption
7.13
Typical Characteristics (Mono Mode): fSPK_AMP = 384 kHz
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.2.1
Functional Block Diagram
9.3
Feature Description
9.3.1
Power Supplies
9.3.2
Speaker Amplifier Audio Signal Path
9.3.2.1
Serial Audio Port (SAP)
9.3.2.1.1
I²S Timing
9.3.2.1.2
Left-Justified
9.3.2.1.3
Right-Justified
9.3.2.2
DC Blocking Filter
9.3.2.3
Digital Boost and Volume Control
9.3.2.4
Digital Clipper
9.3.2.5
Closed-Loop Class-D Amplifier
9.3.3
Speaker Amplifier Protection Suite
9.3.3.1
Speaker Amplifier Fault Notification (SPK_FAULT Pin)
9.3.3.2
DC Detect Protection
9.4
Device Functional Modes
9.4.1
Hardware Control Mode
9.4.1.1
Speaker Amplifier Shut Down (SPK_SD Pin)
9.4.1.2
Serial Audio Port in Hardware Control Mode
9.4.1.3
Soft Clipper Control (SFT_CLIP Pin)
9.4.1.4
Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
9.4.1.5
Hardware Control Mode Select (HW/SCL Pin)
9.4.1.6
Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
9.4.1.7
Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
9.4.1.8
Considerations for Setting the Speaker Amplifier Gain Structure
9.4.1.8.1
Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
9.4.2
Software Control Mode
9.4.2.1
Speaker Amplifier Shut Down (SPK_SD Pin)
9.4.2.2
Serial Audio Port Controls
9.4.2.2.1
Serial Audio Port (SAP) Clocking
9.4.2.3
Channel Select via Software Control
9.4.2.4
Speaker Amplifier Gain Structure
9.4.2.4.1
Speaker Amplifier Gain in Software Control Mode
9.4.2.5
I²C Software Control Port
9.4.2.5.1
Setting the I²C Device Address
9.4.2.5.2
General Operation of the I²C Control Port
9.4.2.5.3
Writing to the I²C Control Port
9.4.2.5.4
Reading from the I²C Control Port
9.5
Register Maps
9.5.1
Control Port Registers - Quick Reference
9.5.2
Control Port Registers - Detailed Description
9.5.2.1
Device Identification Register (0x00)
Table 9.
Device Identification Register Field Descriptions
9.5.2.2
Power Control Register (0x01)
Table 10.
Power Control Register Field Descriptions
9.5.2.3
Digital Control Register (0x02)
Table 11.
Digital Control Register Field Descriptions
9.5.2.4
Volume Control Configuration Register (0x03)
Table 12.
Volume Control Configuration Register Field Descriptions
9.5.2.5
Left Channel Volume Control Register (0x04)
Table 13.
Left Channel Volume Control Register Field Descriptions
9.5.2.6
Right Channel Volume Control Register (0x05)
Table 14.
Right Channel Volume Control Register Field Descriptions
9.5.2.7
Analog Control Register (0x06)
Table 15.
Analog Control Register Field Descriptions
9.5.2.8
Reserved Register (0x07)
9.5.2.9
Fault Configuration and Error Status Register (0x08)
Table 16.
Fault Configuration and Error Status Register Field Descriptions
9.5.2.10
Reserved Controls (9 / 0x09) - (15 / 0x0F)
9.5.2.11
Digital Clipper Control 2 Register (0x10)
Table 17.
Digital Clipper Control 2 Register Field Descriptions
9.5.2.12
Digital Clipper Control 1 Register (0x11)
Table 18.
Digital Clipper Control 1 Register Field Descriptions
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Mono Output Using Software Control
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.2.1
Startup Procedures- Software Control Mode
10.2.1.2.2
Shutdown Procedures- Software Control Mode
10.2.1.2.3
Component Selection and Hardware Connections
10.2.1.2.3.1
I²C Pull-Up Resistors
10.2.1.2.3.2
Digital I/O Connectivity
10.2.2
Mono Output Using Hardware Control
10.2.2.1
Design Requirements
10.2.2.2
Detailed Design Procedure
10.2.2.2.1
Startup Procedures- Hardware Control Mode
10.2.2.2.2
Shutdown Procedures- Hardware Control Mode
10.2.2.2.3
Digital I/O Connectivity
10.2.2.3
Application Curves
11
Power Supply Recommendations
11.1
DVDD Supply
11.2
PVDD Supply
12
Layout
12.1
Layout Guidelines
12.1.1
General Guidelines for Audio Amplifiers
12.1.2
Importance of PVDD Bypass Capacitor Placement on PVDD Network
12.1.3
Optimizing Thermal Performance
12.1.3.1
Device, Copper, and Component Layout
12.1.3.2
Stencil Pattern
12.1.3.2.1
PCB Footprint and Via Arrangement
12.1.3.2.1.1
Solder Stencil
12.2
Layout Example
13
デバイスおよびドキュメントのサポート
13.1
ドキュメントのサポート
13.1.1
関連資料
13.2
サポート・リソース
13.3
商標
13.4
静電気放電に関する注意事項
13.5
Glossary
14
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DAP|32
MPDS380A
サーマルパッド・メカニカル・データ
DAP|32
PPTD231B
発注情報
jajsft0b_oa
jajsft0b_pm
7
Specifications