JAJSE48C August   2017  – April 2018 TAS5755M

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      効率と合計出力電力との関係
      2.      出力電力と電源電圧との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  PWM Operation at Recommended Operating Conditions
    6. 8.6  DC Electrical Characteristics
    7. 8.7  AC Electrical Characteristics (BTL, PBTL)
    8. 8.8  Electrical Characteristics - PLL External Filter Components
    9. 8.9  Electrical Characteristic - I2C Serial Control Port Operation
    10. 8.10 Timing Requirements - PLL Input Parameters
    11. 8.11 Timing Requirements - Serial Audio Ports Slave Mode
    12. 8.12 Timing Requirements - I2C Serial Control Port Operation
    13. 8.13 Timing Requirements - Reset (RESET)
    14. 8.14 Typical Characteristics
      1. 8.14.1 Typical Characteristics, 2.1 SE Configuration
      2. 8.14.2 Typical Characteristics, 2.0 BTL Configuration
      3. 8.14.3 Typical Characteristics, PBTL Configuration
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1  Power Supply
      2. 10.3.2  I2C Address Selection and Fault Output
      3. 10.3.3  Single-Filter PBTL Mode
      4. 10.3.4  Device Protection System
        1. 10.3.4.1 Overcurrent (OC) Protection With Current Limiting
        2. 10.3.4.2 Overtemperature Protection
        3. 10.3.4.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
      5. 10.3.5  SSTIMER Functionality
      6. 10.3.6  Clock, Autodetection, and PLL
      7. 10.3.7  PWM Section
      8. 10.3.8  2.1-Mode Support
      9. 10.3.9  I2C Compatible Serial Control Interface
      10. 10.3.10 Audio Serial Interface
        1. 10.3.10.1 I2S Timing
        2. 10.3.10.2 Left-Justified
        3. 10.3.10.3 Right-Justified
      11. 10.3.11 Dynamic Range Control (DRC)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Stereo BTL Mode
      2. 10.4.2 Mono PBTL Mode
      3. 10.4.3 2.1 Mode
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Control Interface
        1. 10.5.1.1 General I2C Operation
        2. 10.5.1.2 Single- and Multiple-Byte Transfers
        3. 10.5.1.3 Single-Byte Write
        4. 10.5.1.4 Multiple-Byte Write
        5. 10.5.1.5 Single-Byte Read
        6. 10.5.1.6 Multiple-Byte Read
      2. 10.5.2 26-Bit 3.23 Number Format
    6. 10.6 Register Maps
      1. 10.6.1 Register Map Summary
      2. 10.6.2 Register Maps
        1. 10.6.2.1  Clock Control Register (0x00)
        2. 10.6.2.2  Device ID Register (0x01)
        3. 10.6.2.3  Error Status Register (0x02)
        4. 10.6.2.4  System Control Register 1 (0x03)
        5. 10.6.2.5  Serial Data Interface Register (0x04)
        6. 10.6.2.6  System Control Register 2 (0x05)
        7. 10.6.2.7  Soft Mute Register (0x06)
        8. 10.6.2.8  Volume Registers (0x07, 0x08, 0x09, 0x0A)
        9. 10.6.2.9  Volume Configuration Register (0x0E)
        10. 10.6.2.10 Modulation Limit Register (0x10)
        11. 10.6.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
        12. 10.6.2.12 PWM Shutdown Group Register (0x19)
        13. 10.6.2.13 Start/Stop Period Register (0x1A)
        14. 10.6.2.14 Oscillator Trim Register (0x1B)
        15. 10.6.2.15 BKND_ERR Register (0x1C)
        16. 10.6.2.16 Input Multiplexer Register (0x20)
        17. 10.6.2.17 Channel 4 Source Select Register (0x21)
        18. 10.6.2.18 PWM Output Mux Register (0x25)
        19. 10.6.2.19 DRC Control Register (0x46)
        20. 10.6.2.20 Bank Switch and EQ Control Register (0x50)
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Stereo Bridge Tied Load Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 Component Selection and Hardware Connections
          2. 11.2.1.2.2 I2C Pullup Resistors
          3. 11.2.1.2.3 Digital I/O Connectivity
          4. 11.2.1.2.4 Recommended Start-Up and Shutdown Procedures
            1. 11.2.1.2.4.1 Initialization Sequence
            2. 11.2.1.2.4.2 Normal Operation
            3. 11.2.1.2.4.3 Shutdown Sequence
            4. 11.2.1.2.4.4 Power-Down Sequence
        3. 11.2.1.3 Application Curves
      2. 11.2.2 Mono Parallel Bridge Tied Load Application
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
      3. 11.2.3 2.1 Application
        1. 11.2.3.1 Design Requirements
        2. 11.2.3.2 Detailed Design Procedure
        3. 11.2.3.3 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 DVDD and AVDD Supplies
    2. 12.2 PVDD Power Supply
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Examples
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 開発サポート
    2. 14.2 ドキュメントのサポート
      1. 14.2.1 関連資料
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.3.1 Power Supply

To facilitate system design, the TAS5755M needs only a 3.3-V supply in addition to the PVDD power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.

In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical half-bridges with separate bootstrap pins (BST_x). The gate-drive voltage (GVDD_OUT) is derived from the PVDD voltage. Special attention must be paid to placing all decoupling capacitors as close to their associated pins as possible. Inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_OUT) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 288 kHz to 384 kHz, it is recommended to use 10-nF, X7R ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 10-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.

Special attention must be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.

The TAS5755M is fully protected against erroneous power-stage turnon due to parasitic gate charging.