JAJSGO9C July   2013  – May  2017 TAS5760L

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
      2.      出力電力とPVDDとの関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital I/O Pins
    6. 6.6  Master Clock
    7. 6.7  Serial Audio Port
    8. 6.8  Protection Circuitry
    9. 6.9  Speaker Amplifier in All Modes
    10. 6.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode
    11. 6.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode
    12. 6.12 I²C Control Port
    13. 6.13 Typical Idle, Mute, Shutdown, Operational Power Consumption
    14. 6.14 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode)
    15. 6.15 Typical Performance Characteristics (Mono PBTL Mode)
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Speaker Amplifier Audio Signal Path
        1. 8.3.2.1 Serial Audio Port (SAP)
          1. 8.3.2.1.1 I²S Timing
          2. 8.3.2.1.2 Left-Justified
          3. 8.3.2.1.3 Right-Justified
        2. 8.3.2.2 DC Blocking Filter
        3. 8.3.2.3 Digital Boost and Volume Control
        4. 8.3.2.4 Digital Clipper
        5. 8.3.2.5 Closed-Loop Class-D Amplifier
      3. 8.3.3 Speaker Amplifier Protection Suite
        1. 8.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 8.3.3.2 DC Detect Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Control Mode
        1. 8.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 8.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 8.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 8.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 8.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
        6. 8.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 8.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 8.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 8.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 8.4.2 Software Control Mode
        1. 8.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 8.4.2.2 Serial Audio Port Controls
          1. 8.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 8.4.2.3 Parallel Bridge Tied Load Mode via Software Control
        4. 8.4.2.4 Speaker Amplifier Gain Structure
          1. 8.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
          2. 8.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure
          3. 8.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
        5. 8.4.2.5 I²C Software Control Port
          1. 8.4.2.5.1 Setting the I²C Device Address
          2. 8.4.2.5.2 General Operation of the I²C Control Port
          3. 8.4.2.5.3 Writing to the I²C Control Port
          4. 8.4.2.5.4 Reading from the I²C Control Port
    5. 8.5 Register Maps
      1. 8.5.1 Control Port Registers - Quick Reference
      2. 8.5.2 Control Port Registers - Detailed Description
        1. 8.5.2.1  Device Identification Register (0x00)
          1. Table 9. Device Identification Register Field Descriptions
        2. 8.5.2.2  Power Control Register (0x01)
          1. Table 10. Power Control Register Field Descriptions
        3. 8.5.2.3  Digital Control Register (0x02)
          1. Table 11. Digital Control Register Field Descriptions
        4. 8.5.2.4  Volume Control Configuration Register (0x03)
          1. Table 12. Volume Control Configuration Register Field Descriptions
        5. 8.5.2.5  Left Channel Volume Control Register (0x04)
          1. Table 13. Left Channel Volume Control Register Field Descriptions
        6. 8.5.2.6  Right Channel Volume Control Register (0x05)
          1. Table 14. Right Channel Volume Control Register Field Descriptions
        7. 8.5.2.7  Analog Control Register (0x06)
          1. Table 15. Analog Control Register Field Descriptions
        8. 8.5.2.8  Reserved Register (0x07)
        9. 8.5.2.9  Fault Configuration and Error Status Register (0x08)
          1. Table 16. Fault Configuration and Error Status Register Field Descriptions
        10. 8.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 8.5.2.11 Digital Clipper Control 2 Register (0x10)
          1. Table 17. Digital Clipper Control 2 Register Field Descriptions
        12. 8.5.2.12 Digital Clipper Control 1 Register (0x11)
          1. Table 18. Digital Clipper Control 1 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Using Software Control
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Startup Procedures- Software Control Mode
          2. 9.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 9.2.1.2.3 Component Selection and Hardware Connections
            1. 9.2.1.2.3.1 I²C Pullup Resistors
            2. 9.2.1.2.3.2 Digital I/O Connectivity
          4. 9.2.1.2.4 Recommended Startup and Shutdown Procedures
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Stereo BTL Using Hardware Control
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 9.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 9.2.2.2.3 Digital I/O Connectivity
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Mono PBTL Using Software Control
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Startup Procedures- Software Control Mode
          2. 9.2.3.2.2 Shutdown Procedures- Software Control Mode
          3. 9.2.3.2.3 Component Selection and Hardware Connections
            1. 9.2.3.2.3.1 I²C Pull-Up Resistors
            2. 9.2.3.2.3.2 Digital I/O Connectivity
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Mono PBTL Using Hardware Control
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Startup Procedures- Hardware Control Mode
          2. 9.2.4.2.2 Shutdown Procedures- Hardware Control Mode
          3. 9.2.4.2.3 Component Selection and Hardware Connections
          4. 9.2.4.2.4 Digital I/O Connectivity
        3. 9.2.4.3 Application Curve
      5. 9.2.5 Stereo BTL Using Software Control, 32-Pin DAP Package Option
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
          1. 9.2.5.2.1 Startup Procedures- Software Control Mode
          2. 9.2.5.2.2 Shutdown Procedures- Software Control Mode
          3. 9.2.5.2.3 Component Selection and Hardware Connections
            1. 9.2.5.2.3.1 I²C Pullup Resistors
            2. 9.2.5.2.3.2 Digital I/O Connectivity
          4. 9.2.5.2.4 Recommended Startup and Shutdown Procedures
        3. 9.2.5.3 Application Curve
      6. 9.2.6 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
        1. 9.2.6.1 Design Requirements
        2. 9.2.6.2 Detailed Design Procedure
          1. 9.2.6.2.1 Startup Procedures- Hardware Control Mode
          2. 9.2.6.2.2 Shutdown Procedures- Hardware Control Mode
          3. 9.2.6.2.3 Digital I/O Connectivity
        3. 9.2.6.3 Application Curve
      7. 9.2.7 Mono PBTL Using Software Control, 32-Pin DAP Package Option
        1. 9.2.7.1 Design Requirements
        2. 9.2.7.2 Detailed Design Procedure
          1. 9.2.7.2.1 Startup Procedures- Software Control Mode
          2. 9.2.7.2.2 Shutdown Procedures- Software Control Mode
          3. 9.2.7.2.3 Component Selection and Hardware Connections
            1. 9.2.7.2.3.1 I²C Pull-Up Resistors
            2. 9.2.7.2.3.2 Digital I/O Connectivity
        3. 9.2.7.3 Application Curves
      8. 9.2.8 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option
        1. 9.2.8.1 Design Requirements
        2. 9.2.8.2 Detailed Design Procedure
          1. 9.2.8.2.1 Startup Procedures- Hardware Control Mode
          2. 9.2.8.2.2 Shutdown Procedures- Hardware Control Mode
          3. 9.2.8.2.3 Component Selection and Hardware Connections
          4. 9.2.8.2.4 Digital I/O Connectivity
        3. 9.2.8.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB Footprint and Via Arrangement
            1. 11.1.3.2.1.1 Solder Stencil
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode

input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICN(SPK) Idle Channel Noise PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, A-Weighted		 - 66 - µVrms
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted		 - 75 - µVrms
PO(SPK) Maximum Instantaneous Output Power Per. Ch. PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 4Ω, THD+N = 0.1%, 		- 14.2 - W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, THD+N = 0.1%		 - 8 - W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%, 		- 21.9 - W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%		 - 12.5 - W
PO(SPK) Maximum Continuous Output Power Per. Ch.(1) PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 4Ω, THD+N = 0.1%, 		- 14 - W
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, THD+N = 0.1%		 - 8 - W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, THD+N = 0.1%, 		- 13.25 - W
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, THD+N = 0.1%		 - 12.5 - W
SNR(SPK) Signal to Noise Ratio (Referenced to THD+N = 1%) PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, A-Weighted, -60dBFS Input		 - 99.7 - dB
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, A-Weighted, -60dBFS Input		 - 98.2 - dB
THD+N(SPK) Total Harmonic Distortion and Noise PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 4Ω, Po = 1 W		 - 0.02% -
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, Po = 1 W		 - 0.03% -
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 4Ω, Po = 1 W		 - 0.03% -
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, Po = 1 W		 - 0.03% -
X-Talk(SPK) Cross-talk (worst case between LtoR and RtoL coupling) PVDD = 12 V, SPK_GAIN[1:0] Pins = 00,
RSPK = 8Ω, Input Signal 250 mVrms, 1kHz Sine		 - -92 - dB
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01,
RSPK = 8Ω, Input Signal 250 mVrms, 1kHz Sine		 - -93 - dB
(1) The continuous power output of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on it by the system around it, such as the PCB configuration and the ambient operating temperature. The performance characteristics listed in this section are achievable on the TAS5760L's EVM, which is representative of the poplular "2 Layers / 1oz Copper" PCB configuration in a size that is representative of the amount of area often provided to the amplifier section of popular consumer audio electronics. As can be seen in the instantaneous power portion of this table, more power can be delivered from the TAS5760L if steps are taken to pull more heat out of the device. For instance, using a board with more layers or adding a small heatsink will result in an increase of continuous power, up to and including the instantaneous power level. This behavior can also been seen in the POUT vs. PVDD plots shown in the typical performance plots section of this data sheet.