JAJSGO9C July 2013 – May 2017 TAS5760L
PRODUCTION DATA.
As shown in Figure 46, a data-read transfer begins with the master device transmitting a START condition, followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5760L address and the read/write bit, TAS5760L responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another START condition followed by the TAS5760L address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5760L again responds with an acknowledge bit. Next, the TAS5760L transmits the data byte from the register being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a STOP condition to complete the data-read transfer.