SLOSEA8 Data sheet

SLOSEA8 December 2024 TAS5815

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PWP|28
- MPDS373B

サーマルパッド・メカニカル・データ

PWP|28
- PPTD351

発注情報

8.1 CONTROL PORT Registers

Table 8-1 lists the memory-mapped registers for the CONTROL_PORT registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified.

Table 8-1 CONTROL_PORT Registers

Offset	Acronym	Register Name	Section
1h	RESET_CTRL	Reset control	Go
2h	DEVICE_CTRL1	Device control 1	Go
3h	DEVICE_CTRL2	Device control 2	Go
Fh	I2C_PAGE_AUTO_INC	I2C DSP memory access page auto increment	Go
28h	SIG_CH_CTRL	Signal chain control	Go
29h	CLOCK_DET_CTRL	Clock detection control	Go
30h	SDOUT_SEL	SDOUT selection	Go
31h	I2S_CTRL	I2S control 0	Go
33h	SAP_CTRL1	I2S control 1	Go
34h	SAP_CTRL2	I2S control 2	Go
35h	SAP_CTRL3	I2S control 3	Go
37h	FS_MON	FS monitor	Go
38h	BCLK_MON	Bclk monitor	Go
39h	CLKDET_STATUS	Clock detection status	Go
40h	DSP_PGM_MODE	DSP program mode	Go
46h	DSP_CTRL	DSP control	Go
4Ch	DAC_GAIN_LEFT	Left digital volume	Go
4Dh	DAC_GAIN_RIGHT	Right digital volume	Go
4Eh	DIG_VOL_CTRL2	Digital volume control 2	Go
4Fh	DIG_VOL_CTRL3	Digital volume control 3	Go
50h	AUTO_MUTE_CTRL	Auto mute control	Go
51h	AUTO_MUTE_TIME	Auto mute time	Go
53h	ANA_CTRL	Analog control	Go
54h	AGAIN	Analog gain	Go
60h	ADR_CTRL	ADR control	Go
61h	ADR_SEL	ADR output selection	Go
66h	DSP_MISC	DSP misc data	Go
67h	DIE_ID	DIE ID	Go
68h	POWER_STATE	Power State	Go
69h	AUTOMUTE_STATE	Auto mute state	Go
6Ah	RAMP_PHASE_CTRL	Switching clock phase control	Go
6Bh	RAMP_SS_CTRL0	Spread spectrum control 0	Go
6Ch	RAMP_SS_CTRL1	Spread spectrum control 1	Go
70h	CHAN_FAULT	Channel fault	Go
71h	GLOBAL_FAULT1	Global fautl 1	Go
72h	GLOBAL_FAULT2	Global fautl 2	Go
73h	OT_WARNING	OT Warning	Go
74h	PIN_CONTROL1	Pin control 1	Go
75h	PIN_CONTROL2	Pin control 2	Go
76h	MISC_CONTROL	Miscellaneous control	Go
78h	FAULT_CLEAR	Fault clear	Go
79h	OLD_CONTROL	Open load detection control	Go
7Ah	SLD_CONTROL1	Short load detection control 1	Go
7Bh	SLD_CONTROL2	Short load detection control 2	Go
7Ch	LD_REPORT	Load detection report	Go

Complex bit access types are encoded to fit into small table cells. Table 8-2 shows the codes that are used for access types in this section.

Table 8-2 CONTROL_PORT Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.1.1 RESET_CTRL Register (Offset = 1h) [Reset = 00h]

RESET_CTRL is shown in Figure 8-1 and described in Table 8-3.

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Reset control

Figure 8-1 RESET_CTRL Register

7	6	5	4	3	2	1	0
RESERVED			RST_MOD	RESERVED			RST_REG
W-0h			W-0h	W-0h			W-0h

Table 8-3 RESET_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	W	0h
4	RST_MOD	W	0h	WRITE CLEAR BIT Reset Modules This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP. This bit is auto cleared and can be set only in hiz mode. 0: Normal 1: Reset modules
3-1	RESERVED	W	0h
0	RST_REG	W	0h	WRITE CLEAR BIT Reset Registers This bit resets the mode registers back to their initial values. The RAM content is not cleared. This bit is auto cleared and must be set only when the DAC is in hiz mode (resetting registers when the DAC is running is prohibited and not supported) 0: Normal 1: Reset mode registers

8.1.2 DEVICE_CTRL1 Register (Offset = 2h) [Reset = 00h]

DEVICE_CTRL1 is shown in Figure 8-2 and described in Table 8-4.

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Device control 1

Figure 8-2 DEVICE_CTRL1 Register

7	6	5	4	3	2	1	0
RESERVED	FSW_SEL			RESERVED	PBTL_MODE	MODULATION
R/W-0h	R/W-0h			R/W-0h	R/W-0h	R/W-0h

Table 8-4 DEVICE_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0h
6-4	FSW_SEL	R/W	0h	Select PWM switching frequency(Fsw) 3'b 000:768kHz 3'b 001:384kHz 3'b 101:1.024MHz Others reserved
3	RESERVED	R/W	0h
2	PBTL_MODE	R/W	0h	0: Set device to BTL mode 1:Set device to PBTL mode
1-0	MODULATION	R/W	0h	00:BD mode 01:1SPW mode 10:Hybrid mode 11: Reserved

8.1.3 DEVICE_CTRL2 Register (Offset = 3h) [Reset = 10h]

DEVICE_CTRL2 is shown in Figure 8-3 and described in Table 8-5.

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Device control 2

Figure 8-3 DEVICE_CTRL2 Register

7	6	5	4	3	2	1	0
RESERVED			DSP_RST	CH1_MUTE	CH2_MUTE	STATE_CTL
R/W-0h			R/W-1h	R/W-0h	R/W-0h	R/W-0h

Table 8-5 DEVICE_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	0h
4	DSP_RST	R/W	1h	DSP reset When the bit is made 0, DSP will start powering up and send out data. This needs to be made 0 only after all the input clocks are settled so that DMA channels do not go out of sync. 0: Normal operation 1: Reset the DSP
3	CH1_MUTE	R/W	0h	Mute Channel 1 This bit issues soft mute request for the ch1. The volume will be smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute
2	CH2_MUTE	R/W	0h	Mute Channel 2 This bit issues soft mute request for the ch2. The volume will be smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute
1-0	STATE_CTL	R/W	0h	Device state control register 00: Deep Sleep 01: Sleep 10: Hi-Z 11: PLAY

8.1.4 I2C_PAGE_AUTO_INC Register (Offset = Fh) [Reset = 00h]

I2C_PAGE_AUTO_INC is shown in Figure 8-4 and described in Table 8-6.

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I2C DSP memory access page auto increment

Figure 8-4 I2C_PAGE_AUTO_INC Register

7	6	5	4	3	2	1	0
RESERVED				PAGE_INC	RESERVED
R/W-0h				R/W-0h	R/W-0h

Table 8-6 I2C_PAGE_AUTO_INC Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0h
3	PAGE_INC	R/W	0h	Page auto increment disable Disable page auto increment mode. for non-zero books. When end of page is reached it goes back to 8th address location of next page when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in older part. 0: Enable Page auto increment 1: Disable Page auto increment
2-0	RESERVED	R/W	0h

8.1.5 SIG_CH_CTRL Register (Offset = 28h) [Reset = 00h]

SIG_CH_CTRL is shown in Figure 8-5 and described in Table 8-7.

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Signal chain control

Figure 8-5 SIG_CH_CTRL Register

7	6	5	4	3	2	1	0
BCLK_RATIO				FS_MODE
R/W-0h				R/W-0h

Table 8-7 SIG_CH_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	BCLK_RATIO	R/W	0h	These bits indicate the configured BCLK ratio, the number of BCLK clocks in one audio frame. 4'b0000: Auto detection 4'b0011:32FS 4'b0101:64FS 4'b0111:128FS 4'b1001:256FS 4'b1011:512FS Others reserved.
3-0	FS_MODE	R/W	0h	FS Speed Mode These bits select the FS operation mode, which must be set according to the current audio sampling rate. 4’b0000 Auto detection 4’b0110 32kHz 4’b1000 44.1kHz 4’b1001 48kHz 4'b1010 88.2kHz 4’b1011 96kHz Others Reserved

8.1.6 CLOCK_DET_CTRL Register (Offset = 29h) [Reset = 00h]

CLOCK_DET_CTRL is shown in Figure 8-6 and described in Table 8-8.

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Clock detection control

Figure 8-6 CLOCK_DET_CTRL Register

7	6	5	4	3	2	1	0
RESERVED	DET_PLL	BCLK_RANGE	DET_FS	DET_BCLK	DET_BCLKMISS	RESERVED
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 8-8 CLOCK_DET_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0h
6	DET_PLL	R/W	0h	Ignore PLL overate Detection This bit controls whether to ignore the PLL overrate detection. The PLL must be slow than 150MHz or an error will be reported. When ignored, a PLL overrate error will not cause a clock error. 0: Regard PLL overrate detection 1: Ignore PLL overrate detection
5	BCLK_RANGE	R/W	0h	Ignore BCLK Range Detection This bit controls whether to ignore the BCLK range detection. The BCLK must be stable between 256kHz and 50MHz or an error will be reported. When ignored, a BCLK range error will not cause a clock error. 0: Regard BCLK Range detection 1: Ignore BCLK Range detection
4	DET_FS	R/W	0h	Ignore FS Error Detection This bit controls whether to ignore the FS Error detection. When ignored, FS error will not cause a clock error. But CLKDET_STATUS will report fs error. 0: Regard FS detection 1: Ignore FS detection
3	DET_BCLK	R/W	0h	Ignore BCLK Detection This bit controls whether to ignore the BCLK detection against LRCLK. The BCLK must be stable between 32FS and 512FS inclusive or an error will be reported. When ignored, a BCLK error will not cause a clock error. 0: Regard BCLK detection 1: Ignore BCLK detection
2	DET_BCLKMISS	R/W	0h	Ignore BCLK Missing Detection This bit controls whether to ignore the BCLK missing detection. When ignored an BCLK missing will not cause a clock error. 0: Regard BCLK missing detection 1: Ignore BCLK missing detection
1-0	RESERVED	R/W	0h

8.1.7 SDOUT_SEL Register (Offset = 30h) [Reset = 04h]

SDOUT_SEL is shown in Figure 8-7 and described in Table 8-9.

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SDOUT selection

Figure 8-7 SDOUT_SEL Register

7	6	5	4	3	2	1	0
RESERVED					CLASSH_LOGIC	SDOUT_MOD	SDOUT_SEL
R/W-0h					R/W-1h	R/W-0h	R/W-0h

Table 8-9 SDOUT_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	0h
2	CLASSH_LOGIC	R/W	1h	When classH enable, device is not in play state 01: Set the SDOUT PIN to high 00: Set the SDOUT PIN to low
1	SDOUT_MOD	R/W	0h	Set SDOUT as open drain. This bit only applies to GPO functions with Output push-pull mode and has no effect on functions that use Open Drain mode by default 0: Output Push-pull mode 1: Open drain mode
0	SDOUT_SEL	R/W	0h	SDOUT Select This bit selects what is being output as SDOUT via GPIO pins. 0: SDOUT is the DSP output (post-processing) 1: SDOUT is the DSP input (pre-processing)

8.1.8 I2S_CTRL Register (Offset = 31h) [Reset = 00h]

I2S_CTRL is shown in Figure 8-8 and described in Table 8-10.

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I2S control 0

Figure 8-8 I2S_CTRL Register

7	6	5	4	3	2	1	0
RESERVED		BCLK_INV	RESERVED
R/W-0h		R/W-0h	R/W-0h

Table 8-10 I2S_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	0h
5	BCLK_INV	R/W	0h	BCLK Polarity This bit sets the inverted BCLK mode. In inverted BCLK mode, the DAC assumes that the LRCLK and DIN edges are aligned to the rising edge of the BCLK. Normally they are assumed to be aligned to the falling edge of the BCLK. 0: Normal BCLK mode 1: Inverted BCLK mode
4-0	RESERVED	R/W	0h

8.1.9 SAP_CTRL1 Register (Offset = 33h) [Reset = 02h]

SAP_CTRL1 is shown in Figure 8-9 and described in Table 8-11.

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I2S control 1

Figure 8-9 SAP_CTRL1 Register

7	6	5	4	3	2	1	0
SHIFT_MSB	RESERVED	DATA_FMT		LRCLK_PULSE		FRAME_LENGTH
R/W-0h	R/W-0h	R/W-0h		R/W-0h		R/W-2h

Table 8-11 SAP_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SHIFT_MSB	R/W	0h	I2S Shift MSB. Combine with the 8 bits in low register 34h.
6	RESERVED	R/W	0h
5-4	DATA_FMT	R/W	0h	I2S Data Format These bits control both input and output audio interface formats for DAC operation. 00: I2S 01: DSP/TDM 10: RTJ 11: LTJ
3-2	LRCLK_PULSE	R/W	0h	If the LRCLK pulse is shorter than 8 x BCLK, set bit 0-1 to '01' Otherwise, keep these bits as default value '00' 00: High width of LRCLK pulse is equal or greater than 8 cycles of BCLK 01: High width of LRCLK pulse is less than 8 cycles of BCLK
1-0	FRAME_LENGTH	R/W	2h	I2S Word Length These bits control both input and output audio interface sample word lengths for DAC operation. 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits

8.1.10 SAP_CTRL2 Register (Offset = 34h) [Reset = 00h]

SAP_CTRL2 is shown in Figure 8-10 and described in Table 8-12.

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I2S control 2

Figure 8-10 SAP_CTRL2 Register

7	6	5	4	3	2	1	0
SHIFT_LSB
R/W-0h

Table 8-12 SAP_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	SHIFT_LSB	R/W	0h	I2S Shift LSB These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of BCLK from the starting (MSB) of audio frame to the starting of the desired audio sample. 8'b00000000: offset = 0 BCLK (no offset) 8'b00000001: ofsset = 1 BCLK 8'b00000010: offset = 2 BCLKs … 8'b11111111: offset = 512 BCLKs

8.1.11 SAP_CTRL3 Register (Offset = 35h) [Reset = 11h]

SAP_CTRL3 is shown in Figure 8-11 and described in Table 8-13.

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I2S control 3

Figure 8-11 SAP_CTRL3 Register

7	6	5	4	3	2	1	0
RESERVED		CH1_DAC		RESERVED		CH2_DAC
R/W-0h		R/W-1h		R/W-0h		R/W-1h

Table 8-13 SAP_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	0h
5-4	CH1_DAC	R/W	1h	Channel 1 DAC Data Path These bits control the channel 1 audio data path connection. 00: Zero data (mute) 01: Ch1 data 10: Ch2 data 11: Reserved (do not set)
3-2	RESERVED	R/W	0h
1-0	CH2_DAC	R/W	1h	Channel 2 DAC Data Path These bits control the channel 2 audio data path connection. 00: Zero data (mute) 01: Ch2 data 10: Ch1 data 11: Reserved (do not set)

8.1.12 FS_MON Register (Offset = 37h) [Reset = 00h]

FS_MON is shown in Figure 8-12 and described in Table 8-14.

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FS monitor

Figure 8-12 FS_MON Register

7	6	5	4	3	2	1	0
RESERVED		BCLKRATION_MSB		FS_MON
R-0h		R-0h		R-0h

Table 8-14 FS_MON Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h
5-4	BCLKRATION_MSB	R	0h	2 MSB of detected BCLK ratio. These bits indicate the currently detected BCLK ratio, the number of BCLK clocks in one audio frame. Combine with the 8 bits in low register 38h. BCLK = 32 FS~512 FS
3-0	FS_MON	R	0h	These bits indicate the currently detected audio sampling rate. 4’b0000 FS Error 4’b0010 8kHz 4’b0100 16kHz 4’b0110 32kHz 4’b1000 Reserved 4’b1001 48kHz 4’b1011 96kHz Others Reserved

8.1.13 BCLK_MON Register (Offset = 38h) [Reset = 00h]

BCLK_MON is shown in Figure 8-13 and described in Table 8-15.

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Bclk monitor

Figure 8-13 BCLK_MON Register

7	6	5	4	3	2	1	0
BCLKRATIO_LSB
R-0h

Table 8-15 BCLK_MON Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	BCLKRATIO_LSB	R	0h	These bits indicate the currently detected BCLK ratio, the number of BCLK clocks in one audio frame. BCLK = 32 FS~512 FS

8.1.14 CLKDET_STATUS Register (Offset = 39h) [Reset = 00h]

CLKDET_STATUS is shown in Figure 8-14 and described in Table 8-16.

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Clock detection status

Figure 8-14 CLKDET_STATUS Register

7	6	5	4	3	2	1	0
RESERVED		BCLK_OVERRATE	PLL_OVERRATE	PLL_LOCKED	BCLK_MISSING	BCLK_VALID	FS_VALID
R-0h		R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 8-16 CLKDET_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h
5	BCLK_OVERRATE	R	0h	This bit indicates whether the BCLK is overrate or underrate. 0: BCLK is underrate 1: BCLK is overrate
4	PLL_OVERRATE	R	0h	This bit indicates whether the PLL is overrate or not. 0: PLL is underrate 1: PLL is overrate
3	PLL_LOCKED	R	0h	This bit indicates whether the PLL is locked or not. The PLL will be reported as unlocked when it is disabled. 0: PLL is locked 1: PLL is not locked
2	BCLK_MISSING	R	0h	This bit indicates whether the BCLK is missing or not. 0: BCLK is normal 1: BCLK is missing
1	BCLK_VALID	R	0h	This bit indicates whether the BCLK is valid or not. The BCLK ratio must be stable and in the range of 32-512FS to be valid. 0: BCLK is valid 1: BCLK is not valid
0	FS_VALID	R	0h	In auto detection mode(reg_fsmode=0),this bit indicated whether the audio sampling rate is valid. In non auto detection mode(reg_fsmode!=0), FS error indicates that configured sampling frequency set by LRCLK(FS) is different with detected sampling frequency. Even if FS Error Detection Ignore is set, this flag will be also asserted. 0: Sampling rate is valid 1: Not valid

8.1.15 DSP_PGM_MODE Register (Offset = 40h) [Reset = 01h]

DSP_PGM_MODE is shown in Figure 8-15 and described in Table 8-17.

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DSP program mode

Figure 8-15 DSP_PGM_MODE Register

7	6	5	4	3	2	1	0
RESERVED				CH1_HIZ	CH2_HIZ	RESERVED
R/W-0h				R/W-0h	R/W-0h	R/W-1h

Table 8-17 DSP_PGM_MODE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0h
3	CH1_HIZ	R/W	0h	0: Normal operation 1: Force CH1 to Hi-Z mode
2	CH2_HIZ	R/W	0h	0: Normal operation 1: Force CH2 to Hi-Z mode
1-0	RESERVED	R/W	1h

8.1.16 DSP_CTRL Register (Offset = 46h) [Reset = 01h]

DSP_CTRL is shown in Figure 8-16 and described in Table 8-18.

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DSP control

Figure 8-16 DSP_CTRL Register

7	6	5	4	3	2	1	0
RESERVED			PROC_RATE	RESERVED
R/W-0h			R/W-0h	R/W-1h

Table 8-18 DSP_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	0h
4	PROC_RATE	R/W	0h	0: 96k processing flow, 2.0 processing SRC enabled 1: 48k processing flow, 2.1 processing flow enabled
3-0	RESERVED	R/W	1h

8.1.17 DAC_GAIN_LEFT Register (Offset = 4Ch) [Reset = 30h]

DAC_GAIN_LEFT is shown in Figure 8-17 and described in Table 8-19.

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Left digital volume

Figure 8-17 DAC_GAIN_LEFT Register

7	6	5	4	3	2	1	0
CH1_PGA
R/W-30h

Table 8-19 DAC_GAIN_LEFT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CH1_PGA	R/W	30h	Channel 1 Volume These bits control the ch1 digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step. 8'b00000000: +24.0 dB 8'b00000001: +23.5 dB … 8'b00101111: +0.5 dB 8'b00110000: 0.0 dB 8'b00110001: -0.5 dB ... 8'b11111110: -103 dB 8'b11111111: Mute

8.1.18 DAC_GAIN_RIGHT Register (Offset = 4Dh) [Reset = 30h]

DAC_GAIN_RIGHT is shown in Figure 8-18 and described in Table 8-20.

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Right digital volume

Figure 8-18 DAC_GAIN_RIGHT Register

7	6	5	4	3	2	1	0
CH2_PGA
R/W-30h

Table 8-20 DAC_GAIN_RIGHT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	CH2_PGA	R/W	30h	Channel 2 Volume These bits control the ch2 digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step. 8'b00000000: +24.0 dB 8'b00000001: +23.5 dB … 8'b00101111: +0.5 dB 8'b00110000: 0.0 dB 8'b00110001: -0.5 dB ... 8'b11111110: -103 dB 8'b11111111: Mute

8.1.19 DIG_VOL_CTRL2 Register (Offset = 4Eh) [Reset = 33h]

DIG_VOL_CTRL2 is shown in Figure 8-19 and described in Table 8-21.

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Digital volume control 2

Figure 8-19 DIG_VOL_CTRL2 Register

7	6	5	4	3	2	1	0
VNDF		VNDS		VNUF		VNUS
R/W-0h		R/W-3h		R/W-0h		R/W-3h

Table 8-21 DIG_VOL_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	VNDF	R/W	0h	Digital Volume Normal Ramp Down Frequency These bits control the frequency of the digital volume updates when the volume is ramping down 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	VNDS	R/W	3h	Digital Volume Normal Ramp Down Frequency These bits control the frequency of the digital volume updates when the volume is ramping down 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
3-2	VNUF	R/W	0h	Digital Volume Normal Ramp Up Frequency These bits control the frequency of the digital volume updates when the volume is ramping up 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly restore the volume (Instant unmute)
1-0	VNUS	R/W	3h	Digital Volume Normal Ramp Up Step These bits control the step of the digital volume updates when the volume is ramping up 00: Increment by 4 dB for each update 01: Increment by 2 dB for each update 10: Increment by 1 dB for each update 11: Increment by 0.5 dB for each update

8.1.20 DIG_VOL_CTRL3 Register (Offset = 4Fh) [Reset = 30h]

DIG_VOL_CTRL3 is shown in Figure 8-20 and described in Table 8-22.

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Digital volume control 3

Figure 8-20 DIG_VOL_CTRL3 Register

7	6	5	4	3	2	1	0
VEDF		VEDS		RESERVED
R/W-0h		R/W-3h		R/W-0h

Table 8-22 DIG_VOL_CTRL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	VEDF	R/W	0h	Digital Volume Emergency Ramp Down Frequency These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute)
5-4	VEDS	R/W	3h	Digital Volume Emergency Ramp Down Step These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update
3-0	RESERVED	R/W	0h

8.1.21 AUTO_MUTE_CTRL Register (Offset = 50h) [Reset = 00h]

AUTO_MUTE_CTRL is shown in Figure 8-21 and described in Table 8-23.

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Auto mute control

Figure 8-21 AUTO_MUTE_CTRL Register

7	6	5	4	3	2	1	0
RESERVED					AM_CTL	AMUTE_CH2	AMUTE_CH1
R/W-0h					R/W-0h	R/W-0h	R/W-0h

Table 8-23 AUTO_MUTE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R/W	0h
2	AM_CTL	R/W	0h	0: Auto mute channel 1 and channel 2 independently 1: Auto mute channel 1 and channel 2 only when both channels are about to be auto muted
1	AMUTE_CH2	R/W	0h	Auto Mute Channel 2 This bit enables or disables auto mute on Channel 2 0: Disable Channel 2 auto mute 1: Enable Channel 2 auto mute
0	AMUTE_CH1	R/W	0h	Auto Mute Channel 1 This bit enables or disables auto mute on Channel 1 0: Disable Channel 1 auto mute 1: Enable Channel 1 auto mute

8.1.22 AUTO_MUTE_TIME Register (Offset = 51h) [Reset = 55h]

AUTO_MUTE_TIME is shown in Figure 8-22 and described in Table 8-24.

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Auto mute time

Figure 8-22 AUTO_MUTE_TIME Register

7	6	5	4	3	2	1	0
RESERVED	CH1_AMT			RESERVED	CH2_AMT
R/W-0h	R/W-5h			R/W-0h	R/W-5h

Table 8-24 AUTO_MUTE_TIME Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0h
6-4	CH1_AMT	R/W	5h	Auto Mute Time for Channel 1 These bits specify the length of consecutive zero samples at ch1 before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec
3	RESERVED	R/W	0h
2-0	CH2_AMT	R/W	5h	Auto Mute Time for Channel 2 These bits specify the length of consecutive zero samples at ch2 before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec

8.1.23 ANA_CTRL Register (Offset = 53h) [Reset = 00h]

ANA_CTRL is shown in Figure 8-23 and described in Table 8-25.

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Analog control

Figure 8-23 ANA_CTRL Register

7	6	5	4	3	2	1	0
RESERVED	BW_CTL		RESERVED				PHASE_CTL
R/W-0h	R/W-0h		R/W-0h				R/W-0h

Table 8-25 ANA_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0h
6-5	BW_CTL	R/W	0h	Class D Loop Bandwidth 00: 100kHz 01: 80kHz 10: 120kHz 11: 175kHz When Fsw=384kHz, 100kHz bandwidth is selected for high audio performance. With Fsw=768kHz, 175kHz bandwidth should be selected for high audio performance.
4-1	RESERVED	R/W	0h
0	PHASE_CTL	R/W	0h	0: Out of phase 1: In phase

8.1.24 AGAIN Register (Offset = 54h) [Reset = 00h]

AGAIN is shown in Figure 8-24 and described in Table 8-26.

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Analog gain

Figure 8-24 AGAIN Register

7	6	5	4	3	2	1	0
RESERVED			AGAIN
R/W-0h			R/W-0h

Table 8-26 AGAIN Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	0h
4-0	AGAIN	R/W	0h	Analog Gain Control This bit controls the analog gain 00000: 0 dB 00001:-0.5 dB …… 11111: -15.5 dB

8.1.25 ADR_CTRL Register (Offset = 60h) [Reset = 00h]

ADR_CTRL is shown in Figure 8-25 and described in Table 8-27.

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ADR control

Figure 8-25 ADR_CTRL Register

7	6	5	4	3	2	1	0
RESERVED							ADR_OE
R/W-0h							R/W-0h

Table 8-27 ADR_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R/W	0h
0	ADR_OE	R/W	0h	ADR Output Enable This bit sets the direction of the ADR pin 0: ADR is input 1: ADR is output

8.1.26 ADR_SEL Register (Offset = 61h) [Reset = 00h]

ADR_SEL is shown in Figure 8-26 and described in Table 8-28.

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ADR output selection

Figure 8-26 ADR_SEL Register

7	6	5	4	3	2	1	0
RESERVED			ADR_SEL
R/W-0h			R/W-0h

Table 8-28 ADR_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R/W	0h
4-0	ADR_SEL	R/W	0h	b'00000: off (low) b'00011: Auto mute flag (asserted when both L and R channels are auto muted) b'00100: Auto mute flag for left channel b'00101: Auto mute flag for right channel b'00110: Clock invalid flag (clock error or clock missing) b'00111: PLL lock flag b'01000: Warning b'01001: Serial audio interface data output (SDOUT) b'01011: ADR as FAULTZ output Others: reserved

8.1.27 DSP_MISC Register (Offset = 66h) [Reset = 00h]

DSP_MISC is shown in Figure 8-27 and described in Table 8-29.

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DSP misc data

Figure 8-27 DSP_MISC Register

7	6	5	4	3	2	1	0
RESERVED		DSP_MISC	RESERVED
R/W-0h		R/W-0h	R/W-0h

Table 8-29 DSP_MISC Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	0h
5	DSP_MISC	R/W	0h	0: Class-H disable 1: Class-H enable
4-0	RESERVED	R/W	0h

8.1.28 DIE_ID Register (Offset = 67h) [Reset = A7h]

DIE_ID is shown in Figure 8-28 and described in Table 8-30.

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DIE ID

Figure 8-28 DIE_ID Register

7	6	5	4	3	2	1	0
DIE_ID
R-A7h

Table 8-30 DIE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DIE_ID	R	A7h	The Die ID for TAS5815

8.1.29 POWER_STATE Register (Offset = 68h) [Reset = 00h]

POWER_STATE is shown in Figure 8-29 and described in Table 8-31.

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Power State

Figure 8-29 POWER_STATE Register

7	6	5	4	3	2	1	0
RESERVED						STATE_RPT
R-0h						R-0h

Table 8-31 POWER_STATE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h
1-0	STATE_RPT	R	0h	00: Deep sleep 01: Sleep 10: Hi-Z 11: Play

8.1.30 AUTOMUTE_STATE Register (Offset = 69h) [Reset = 00h]

AUTOMUTE_STATE is shown in Figure 8-30 and described in Table 8-32.

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Auto mute state

Figure 8-30 AUTOMUTE_STATE Register

7	6	5	4	3	2	1	0
RESERVED						CH2MUTE_STATUS	CH1MUTE_STATUS
R-0h						R-0h	R-0h

Table 8-32 AUTOMUTE_STATE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h
1	CH2MUTE_STATUS	R	0h	This bit indicates the auto mute status for Channel 2. 0: Not auto muted 1: Auto muted
0	CH1MUTE_STATUS	R	0h	This bit indicates the auto mute status for Channel 1. 0: Not auto muted 1: Auto muted

8.1.31 RAMP_PHASE_CTRL Register (Offset = 6Ah) [Reset = 00h]

RAMP_PHASE_CTRL is shown in Figure 8-31 and described in Table 8-33.

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Switching clock phase control

Figure 8-31 RAMP_PHASE_CTRL Register

7	6	5	4	3	2	1	0
RESERVED				RAMPPHASE_SEL		RESERVED
R/W-0h				R/W-0h		R/W-0h

Table 8-33 RAMP_PHASE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R/W	0h
3-2	RAMPPHASE_SEL	R/W	0h	Select ramp clock phase when multi devices are integrated in one system to reduce EMI and peak supply peak current, it is recomended set all devices the same RAMP frequency and same spread spectrum. it must be set before driving device into PLAY mode if this feature is needed. 00: 0 degree 01: 45 degree 10: 90 degree 11: 135 degree all of above have a 45 degree of phase shift
1-0	RESERVED	R/W	0h	Use I2S to synchronize output PWM phase 0: Disable 1: Enable
0	PHASE_SYNC_EN	R/W	0h	0: RAMP phase sync disable 1: RAMP phase sync enable

8.1.32 RAMP_SS_CTRL0 Register (Offset = 6Bh) [Reset = 00h]

RAMP_SS_CTRL0 is shown in Figure 8-32 and described in Table 8-34.

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Spread spectrum control 0

Figure 8-32 RAMP_SS_CTRL0 Register

7	6	5	4	3	2	1	0
RESERVED						RDM_EN	TRI_EN
R/W-0h						R/W-0h	R/W-0h

Table 8-34 RAMP_SS_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R/W	0h
1	RDM_EN	R/W	0h	0: Random SS disable 1: Random SS enable
0	TRI_EN	R/W	0h	0: Triangle SS disable 1: Triangle SS enable

8.1.33 RAMP_SS_CTRL1 Register (Offset = 6Ch) [Reset = 00h]

RAMP_SS_CTRL1 is shown in Figure 8-33 and described in Table 8-35.

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Spread spectrum control 1

Figure 8-33 RAMP_SS_CTRL1 Register

7	6	5	4	3	2	1	0
RESERVED	RDM_CTL			TRI_CTL
R/W-0h	R/W-0h			R/W-0h

Table 8-35 RAMP_SS_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0h
6-4	RDM_CTL	R/W	0h	Random SS range control For Fsw of 384kHz 3'b000: SS range +/- 0.62% 3'b010: SS range +/- 1.88% 3'b011: SS range +/- 4.38% 3'b100: SS range +/- 9.38% 3'b101: SS range +/- 19.38% Others: reserved For Fsw of 768kHz 3'b000: SS range - 1.25% 3'b001: SS range +/- 1.25% 3'b010: SS range +/- 3.75% 3'b011: SS range +/- 8.75% 3'b100: SS range +/- 18.75% 3'b101: SS range +/- 38.75% Others: reserved
3-0	TRI_CTL	R/W	0h	Triangle SS frequency and range control 4'b0000: 24kHz SS +/- 5% 4'b0001: 24kHz SS +/- 10% 4'b0010: 24kHz SS +/- 20% 4'b0011: 24kHz SS +/- 25% 4'b0100: 48kHz SS +/- 5% 4'b0101: 48kHz SS +/- 10% 4'b0110: 48kHz SS +/- 20% 4'b0111: 48kHz SS +/- 25% 4'b1000: 32kHz SS +/- 5% 4'b1001: 32kHz SS +/- 10% 4'b1010: 32kHz SS +/- 20% 4'b1011: 32kHz SS +/- 25% 4'b1100: 16kHz SS +/- 5% 4'b1101: 16kHz SS +/- 10% 4'b1110: 16kHz SS +/- 20% 4'b1111: 16kHz SS +/- 25%

8.1.34 CHAN_FAULT Register (Offset = 70h) [Reset = 00h]

CHAN_FAULT is shown in Figure 8-34 and described in Table 8-36.

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Channel fault

Figure 8-34 CHAN_FAULT Register

7	6	5	4	3	2	1	0
RESERVED				CH1DC	CH2DC	CH1OC	CH2OC
R-0h				R-0h	R-0h	R-0h	R-0h

Table 8-36 CHAN_FAULT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h
3	CH1DC	R	0h	Channel 1 DC fault. Once there is a DC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1.
2	CH2DC	R	0h	Channel 2 DC fault. Once there is a DC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1.
1	CH1OC	R	0h	Channel 1 over current fault. Once there is a OC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1.
0	CH2OC	R	0h	Channel 2 over current fault. Once there is a OC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1.

8.1.35 GLOBAL_FAULT1 Register (Offset = 71h) [Reset = 00h]

GLOBAL_FAULT1 is shown in Figure 8-35 and described in Table 8-37.

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Global fautl 1

Figure 8-35 GLOBAL_FAULT1 Register

7	6	5	4	3	2	1	0
RESERVED	BQWRTFAULT_FLAG	RESERVED			CLKFAULT_FLAG	PVDDOV_FLAG	PVDDUV_FLAG
R-0h	R-0h	R-0h			R-0h	R-0h	R-0h

Table 8-37 GLOBAL_FAULT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	BQWRTFAULT_FLAG	R	0h	0: The recent BQ is written successfully 1: The recent BQ is written failed
5-3	RESERVED	R	0h
2	CLKFAULT_FLAG	R	0h	Clock fault. Once there is a Clock fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clock fault works with an auto-recovery mode, once the clock error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1.
1	PVDDOV_FLAG	R	0h	PVDD OV fault. Once there is a OV fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an auto-recovery mode, once the OV error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1.
0	PVDDUV_FLAG	R	0h	PVDD UV fault. Once there is a UV fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). UV fault works with an auto-recovery mode, once the UV error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1.

8.1.36 GLOBAL_FAULT2 Register (Offset = 72h) [Reset = 00h]

GLOBAL_FAULT2 is shown in Figure 8-36 and described in Table 8-38.

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Global fautl 2

Figure 8-36 GLOBAL_FAULT2 Register

7	6	5	4	3	2	1	0
RESERVED							OTSD_FLAG
R-0h							R-0h

Table 8-38 GLOBAL_FAULT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0h
0	OTSD_FLAG	R	0h	Over temperature shut down fault Once there is a OT fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). OV fault works with an autorecovery mode, once the OV error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1.

8.1.37 OT_WARNING Register (Offset = 73h) [Reset = 00h]

OT_WARNING is shown in Figure 8-37 and described in Table 8-39.

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OT Warning

Figure 8-37 OT_WARNING Register

7	6	5	4	3	2	1	0
RESERVED					OTW_FLAG	RESERVED
R-0h					R-0h	R-0h

Table 8-39 OT_WARNING Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R	0h
2	OTW_FLAG	R	0h	0: No temperature warning 1: Over temperature warning is triggered
1-0	RESERVED	R	0h

8.1.38 PIN_CONTROL1 Register (Offset = 74h) [Reset = 00h]

PIN_CONTROL1 is shown in Figure 8-38 and described in Table 8-40.

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Pin control 1

Figure 8-38 PIN_CONTROL1 Register

7	6	5	4	3	2	1	0
MASK_OTSD	MASK_DVDDUV	MASK_DVDDOV	MASK_CLKERROR	MASK_PVDDUV	MASK_PVDDOV	MASK_DC	MASK_OC
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 8-40 PIN_CONTROL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MASK_OTSD	R/W	0h	0: Enable OTSD fault report 1: Mask OTSD fault report
6	MASK_DVDDUV	R/W	0h	0: Enable DVDD UV fault report 1: Mask DVDD UV report
5	MASK_DVDDOV	R/W	0h	0: Enable DVDD OV fault report 1: Mask DVDD OV fault report
4	MASK_CLKERROR	R/W	0h	0: Enable CLK fault report 1: Mask CLK fault report
3	MASK_PVDDUV	R/W	0h	0: Enable UV fault report 1: Mask UV fault report
2	MASK_PVDDOV	R/W	0h	0: Enable OV fault report 1: Mask OV fault report
1	MASK_DC	R/W	0h	0: Enable DC fault report 1: Mask DC fault report
0	MASK_OC	R/W	0h	0: Enable OC fault report 1: Mask OC fault report

8.1.39 PIN_CONTROL2 Register (Offset = 75h) [Reset = F8h]

PIN_CONTROL2 is shown in Figure 8-39 and described in Table 8-41.

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Pin control 2

Figure 8-39 PIN_CONTROL2 Register

7	6	5	4	3	2	1	0
RESERVED		CLKFAULTLATCH_EN	OTSDLATCH_EN	OTWLATCH_EN	MASK_OTW	RESERVED
R/W-3h		R/W-1h	R/W-1h	R/W-1h	R/W-0h	R/W-0h

Table 8-41 PIN_CONTROL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	3h
5	CLKFAULTLATCH_EN	R/W	1h	0: Disable CLK fault latch 1: Enable CLK fault latch
4	OTSDLATCH_EN	R/W	1h	0: Disable OTSD fault latch 1: Enable OTSD fault latch
3	OTWLATCH_EN	R/W	1h	0: Disable OTW warning latch 1: Enable OTW warning latch
2	MASK_OTW	R/W	0h	0: Enable OTW warning report 1: Mask OTW warning report
1-0	RESERVED	R/W	0h

8.1.40 MISC_CONTROL Register (Offset = 76h) [Reset = 00h]

MISC_CONTROL is shown in Figure 8-40 and described in Table 8-42.

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Miscellaneous control

Figure 8-40 MISC_CONTROL Register

7	6	5	4	3	2	1	0
CLKDET_LATCH	RESERVED		OTSD_AUTOREC	RESERVED
R/W-0h	R/W-0h		R/W-0h	R/W-0h

Table 8-42 MISC_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CLKDET_LATCH	R/W	0h	1:Latch clock detection status 0:No latch clock detection status
6-5	RESERVED	R/W	0h
4	OTSD_AUTOREC	R/W	0h	0: Disable OTSD auto recovery 1: Enable OTSD auto recovery
3-0	RESERVED	R/W	0h

8.1.41 FAULT_CLEAR Register (Offset = 78h) [Reset = 00h]

FAULT_CLEAR is shown in Figure 8-41 and described in Table 8-43.

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Fault clear

Figure 8-41 FAULT_CLEAR Register

7	6	5	4	3	2	1	0
FAULT_CLR	RESERVED
W-0h	W-0h

Table 8-43 FAULT_CLEAR Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FAULT_CLR	W	0h	WRITE CLEAR BIT 0: No fault clear 1: Clear analog fault
6-0	RESERVED	W	0h

8.1.42 OLD_CONTROL Register (Offset = 79h) [Reset = 00h]

OLD_CONTROL is shown in Figure 8-42 and described in Table 8-44.

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Open load detection control

Figure 8-42 OLD_CONTROL Register

7	6	5	4	3	2	1	0
DET_EN	PLUSE_EN	WAIT_TIME		DISCHG_TIME		CHG_TIME
W-0h	R/W-0h	R/W-0h		R/W-0h		R/W-0h

Table 8-44 OLD_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DET_EN	W	0h	0: Open load detection enable 1: Open load detection disable
6	PLUSE_EN	R/W	0h	0: OLD pulse injection disable 1: OLD pulse injection enable
5-4	WAIT_TIME	R/W	0h	00: 0.5 ms 01: 1 ms 10: 2 ms 11: 4 ms
3-2	DISCHG_TIME	R/W	0h	00: 3 ms 01: 6 ms 10: 12 ms 11: 24 ms
1-0	CHG_TIME	R/W	0h	00: 1 ms 01: 2 ms 10: 4 ms 11: 8 ms

8.1.43 SLD_CONTROL1 Register (Offset = 7Ah) [Reset = 09h]

SLD_CONTROL1 is shown in Figure 8-43 and described in Table 8-45.

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Short load detection control 1

Figure 8-43 SLD_CONTROL1 Register

7	6	5	4	3	2	1	0
DET_EN	STATUS_SET	WIN_SET			DUTY_SET
W-0h	W-0h	W-1h			W-1h

Table 8-45 SLD_CONTROL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DET_EN	W	0h	0: Short load detection disable 1: Short load detection enable
6	STATUS_SET	W	0h	0: Exit to PLAY after OL detection 1: Exit to Hi-Z, then return to PLAY once this bit manually cleared
5-3	WIN_SET	W	1h	b'000: 15 us b'001: 20 us b'010:30 us b'011:40 us b'100:50 us b'101:60 us b'110:70 us b'111:80 us
2-0	DUTY_SET	W	1h	b'000: 100% duty square wave b'001: 20% duty square wave b'010:40% duty square wave b'011:50% duty square wave b'100:60% duty square wave b'101:70% duty square wave b'110:80% duty square wave b'111:90% duty square wave

8.1.44 SLD_CONTROL2 Register (Offset = 7Bh) [Reset = 03h]

SLD_CONTROL2 is shown in Figure 8-44 and described in Table 8-46.

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Short load detection control 2

Figure 8-44 SLD_CONTROL2 Register

7	6	5	4	3	2	1	0
DISCHG_TIME		STATUS_SET	RESERVED
R/W-0h		R/W-0h	R/W-3h

Table 8-46 SLD_CONTROL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	DISCHG_TIME	R/W	0h	00: 1 ms 01: 2 ms 10: 4 ms 11: 8 ms
5	STATUS_SET	R/W	0h	0: Exit to PLAY after SL detection 1: Exit to Hi-Z, then return to PLAY once this bit manually cleared
4-0	RESERVED	R/W	3h

8.1.45 LD_REPORT Register (Offset = 7Ch) [Reset = 00h]

LD_REPORT is shown in Figure 8-45 and described in Table 8-47.

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Load detection report

Figure 8-45 LD_REPORT Register

7	6	5	4	3	2	1	0
RESERVED	SLD_STATUS2	SLD_STATUS1	SLDET_FLAG	RESERVED	OLD_STATUS2	OLD_STATUS1	OLDET_FLAG
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 8-47 LD_REPORT Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	SLD_STATUS2	R	0h	0: No short load on Channel 2 1: Short load on Channel 2
5	SLD_STATUS1	R	0h	0: No short load on Channel 1 1: Short load on Channel 1
4	SLDET_FLAG	R	0h	0: Short load detection is on going 1: Short load detection done
3	RESERVED	R	0h
2	OLD_STATUS2	R	0h	0: No open load on Channel 2 1: Open load on Channel 2
1	OLD_STATUS1	R	0h	0: No open load on Channel 1 1: Open load on Channel 1
0	OLDET_FLAG	R	0h	0: Open load detection is on going 1: Open load detection done