JAJSI51A May   2019  – January 2023 TAS5825P

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
      2. 7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
      3. 7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      4. 7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port – Clock Rates
      4. 9.3.4 Clock Halt Auto-Recovery
      5. 9.3.5 Sample Rate on the Fly Change
      6. 9.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 9.3.7 Digital Audio Processing
      8. 9.3.8 Class-D Audio Amplifier
        1. 9.3.8.1 Speaker Amplifier Gain Select
        2. 9.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Software Control
      2. 9.4.2 Speaker Amplifier Operating Modes
        1. 9.4.2.1 BTL Mode
        2. 9.4.2.2 PBTL Mode
      3. 9.4.3 Low EMI Modes
        1. 9.4.3.1 Spread Spectrum
        2. 9.4.3.2 Channel to Channel Phase Shift
        3. 9.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 9.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 9.4.3.3.2 Phase Synchronization With GPIO
      4. 9.4.4 Thermal Foldback
      5. 9.4.5 Device State Control
      6. 9.4.6 Device Modulation
        1. 9.4.6.1 BD Modulation
        2. 9.4.6.2 1SPW Modulation
        3. 9.4.6.3 Hybrid Modulation
    5. 9.5 Programming and Control
      1. 9.5.1 I2 C Serial Communication Bus
      2. 9.5.2 I2 C Peripheral Address
        1. 9.5.2.1 Random Write
        2. 9.5.2.2 Sequential Write
        3. 9.5.2.3 Random Read
        4. 9.5.2.4 Sequential Read
        5. 9.5.2.5 DSP Memory Book, Page and BQ update
        6. 9.5.2.6 Checksum
          1. 9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 9.5.2.6.2 Exclusive or (XOR) Checksum
      3. 9.5.3 Control via Software
        1. 9.5.3.1 Startup Procedures
        2. 9.5.3.2 Shutdown Procedures
        3. 9.5.3.3 Protection and Monitoring
          1. 9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 9.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 9.5.3.3.3 DC Detect
    6. 9.6 Register Maps
      1. 9.6.1 CONTROL PORT Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Bootstrap Capacitors
      2. 10.1.2 Inductor Selections
      3. 10.1.3 Power Supply Decoupling
      4. 10.1.4 Output EMI Filtering
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
      2. 10.2.2 79
      3. 10.2.3 Design Requirements
      4. 10.2.4 Detailed Design procedures
        1. 10.2.4.1 Step One: Hardware Integration
        2. 10.2.4.2 Step Two: Hardware Integration
        3. 10.2.4.3 Step Three: Software Integration
      5. 10.2.5 Application Curves
      6. 10.2.6 MONO (PBTL) Systems
      7. 10.2.7 Application Curves
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 DVDD Supply
      2. 10.3.2 PVDD Supply
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 General Guidelines for Audio Amplifiers
        2. 10.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 10.4.1.3 Optimizing Thermal Performance
          1. 10.4.1.3.1 Device, Copper, and Component Layout
          2. 10.4.1.3.2 Stencil Pattern
            1. 10.4.1.3.2.1 PCB footprint and Via Arrangement
            2. 10.4.1.3.2.2 Solder Stencil
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Development Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.6 Serial Audio Port - Data Formats and Bit Depths

The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and TDM/DSP data. Data formats are selected via Register (Register Address 0x33h -D[5:4]). If the high width of LRCLK/FS in TDM/DSP mode is less than 8 cycles of SCK, then the register (Register Address 0x33h -D[3:2]) sets to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. All the data formats, word length and clock rate supported by this device are shown in Table 1. The data formats are detailed in #SLAS7591578 through #SLAS7593070. The word length are selected via Register (Register Address 0x33h -D[1:0]). The offsets of data are selected via Register (Register Address 0x33h -D[7]) and Register (Register Address 0x34h -D[7:0]). Default setting is I2S and 24 bit word length.

GUID-D9E4E8DB-6609-46E1-B816-FD142116DE4C-low.gifFigure 9-2 Left Justified Audio Data Format
GUID-647B1430-7EAC-4C58-B4CD-6299EC29F5DD-low.gif
I2S Data Format; L-channel = LOW, R-channel = HIGH
Figure 9-3 I2S Audio Data Format
GUID-1231B0C3-6D34-4A85-9904-F722E88BF706-low.gif
Right Justified Data Format; L-channel = HIGH, R-channel = LOW
Figure 9-4 Right Justified Audio Data Format
GUID-A7D2B616-7795-4FAC-9F1D-87498B070B9B-low.gif
TDM Data Format with OFFSET = 0
In TDM Modes, Duty Cycle of LRCK/FS must be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 9-5 TDM 1 Audio Data Format
GUID-C4D5A3C8-6CC4-4630-ADAF-9F55263C1247-low.gif
TDM Data Format with OFFSET = 1
In TDM Modes, Duty Cycle of LRCK/FS must be 1x SCLK at minimum. Rising edge is considered frame start.
Figure 9-6 TDM 2 Audio Data Format