JAJSI51A May   2019  – January 2023 TAS5825P

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
      2. 7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
      3. 7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      4. 7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port – Clock Rates
      4. 9.3.4 Clock Halt Auto-Recovery
      5. 9.3.5 Sample Rate on the Fly Change
      6. 9.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 9.3.7 Digital Audio Processing
      8. 9.3.8 Class-D Audio Amplifier
        1. 9.3.8.1 Speaker Amplifier Gain Select
        2. 9.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Software Control
      2. 9.4.2 Speaker Amplifier Operating Modes
        1. 9.4.2.1 BTL Mode
        2. 9.4.2.2 PBTL Mode
      3. 9.4.3 Low EMI Modes
        1. 9.4.3.1 Spread Spectrum
        2. 9.4.3.2 Channel to Channel Phase Shift
        3. 9.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 9.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 9.4.3.3.2 Phase Synchronization With GPIO
      4. 9.4.4 Thermal Foldback
      5. 9.4.5 Device State Control
      6. 9.4.6 Device Modulation
        1. 9.4.6.1 BD Modulation
        2. 9.4.6.2 1SPW Modulation
        3. 9.4.6.3 Hybrid Modulation
    5. 9.5 Programming and Control
      1. 9.5.1 I2 C Serial Communication Bus
      2. 9.5.2 I2 C Peripheral Address
        1. 9.5.2.1 Random Write
        2. 9.5.2.2 Sequential Write
        3. 9.5.2.3 Random Read
        4. 9.5.2.4 Sequential Read
        5. 9.5.2.5 DSP Memory Book, Page and BQ update
        6. 9.5.2.6 Checksum
          1. 9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 9.5.2.6.2 Exclusive or (XOR) Checksum
      3. 9.5.3 Control via Software
        1. 9.5.3.1 Startup Procedures
        2. 9.5.3.2 Shutdown Procedures
        3. 9.5.3.3 Protection and Monitoring
          1. 9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 9.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 9.5.3.3.3 DC Detect
    6. 9.6 Register Maps
      1. 9.6.1 CONTROL PORT Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Bootstrap Capacitors
      2. 10.1.2 Inductor Selections
      3. 10.1.3 Power Supply Decoupling
      4. 10.1.4 Output EMI Filtering
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
      2. 10.2.2 79
      3. 10.2.3 Design Requirements
      4. 10.2.4 Detailed Design procedures
        1. 10.2.4.1 Step One: Hardware Integration
        2. 10.2.4.2 Step Two: Hardware Integration
        3. 10.2.4.3 Step Three: Software Integration
      5. 10.2.5 Application Curves
      6. 10.2.6 MONO (PBTL) Systems
      7. 10.2.7 Application Curves
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 DVDD Supply
      2. 10.3.2 PVDD Supply
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 General Guidelines for Audio Amplifiers
        2. 10.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 10.4.1.3 Optimizing Thermal Performance
          1. 10.4.1.3.1 Device, Copper, and Component Layout
          2. 10.4.1.3.2 Stencil Pattern
            1. 10.4.1.3.2.1 PCB footprint and Via Arrangement
            2. 10.4.1.3.2.2 Solder Stencil
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Development Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

Free-air room temperature 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Digital I/O
|IIH|Input logic high current level for DVDD referenced digital input pinsVIN(DigIn) = VDVDD10µA
|IIL|Input logic low current level for DVDD referenced digital input pinsVIN(DigIn) = 0 V–10µA
VIH(Digin)Input logic high threshold for DVDD referenced digital inputs70%VDVDD
VIL(Digin)Input logic low threshold for DVDD referenced digital inputs30%VDVDD
VOH(Digin)Output logic high voltage levelIOH = 4 mA80%VDVDD
VOL(Digin)Output logic low voltage levelIOH = –4 mA20%VDVDD
I2C Control Port
CL(I2C)Allowable load capacitance for each I2C Line400pF
fSCL(fast)Support SCL frequencyNo wait states, fast mode400kHz
fSCL(slow)Support SCL frequencyNo wait states, slow mode100kHz
Serial Audio Port
tDLYRequired LRCK/FS to SCLK rising edge delay5ns
DSCLKAllowable SCLK duty cycle40%60%
fSSupported input sample rates32192kHz
fSCLKSupported SCLK frequencies3264fS
fSCLKSCLK frequency24.576MHz
Speaker Amplifier (All Output Configurations)
toffTurn-off TimeExcluding volume ramp10ms
ICCQuiescent supply current of DVDDPDN = 2 V, DVDD = 3.3 V, Play mode,
General Audio Process flow with full DSP running		25.5mA
ICCQuiescent supply current of DVDDPDN = 2 V, DVDD = 3.3 V, Sleep mode0.87mA
ICCQuiescent supply current of DVDDPDN = 2 V, DVDD = 3.3 V, Deep Sleep mode0.82mA
ICCQuiescent supply current of DVDDPDN = 0.8 V, DVDD = 3.3 V, Shutdown mode7.4µA
ICCQuiescent supply current of PVDDPDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 10 µH + 0.68 µF, FSW = 384 kHz, Hybrid Modulation, Play Mode29.5mA
ICCQuiescent supply current of PVDDPDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 22 µH + 0.68 µF, FSW = 384 kHz, Hybrid Modulation, Play Mode20.5mA
ICCQuiescent supply current of PVDDPDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 10 µH + 0.68 µF, FSW = 384 kHz, Output Hiz Mode10.7mA
ICCQuiescent supply current of PVDDPDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 10 µH + 0.68 µF, Fsw = 384 kHz, Sleep Mode7.26mA
ICCQuiescent supply current of PVDDPDN = 2 V, PVDD = 13.5 V, No Load, LC filter = 10 µH + 0.68 µF, Fsw = 384 kHz, Deep Sleep Mode12.01µA
ICCQuiescent supply current of PVDDPDN = 0.8 V, PVDD = 13.5 V, No Load, LC filter = 10 µH + 0.68 µF, FSW = 384 kHz, Shutdown Mode7.8µA
AV(SPK_AMP)Programmable GainValue represents the "peak voltage" disregarding clipping due to lower PVDD).
Measured at 0 dB input (1FS)		4.8729.5V
ΔAV(SPK_AMP)Amplifier gain errorGain = 29.5 VP0.5dB
fSPK_AMPSwitching frequency of the speaker amplifier384kHz
768kHz
RDS(on)Drain-to-source on resistance of the individual output MOSFETsFET + Metallization.90mΩ
OCETHRESOver-Current Error ThresholdAny short to supply, ground, or other channels7.5A
Over-Current cycle-by-cycle limit6.5A
OVETHRES(PVDDPVDD over voltage error threshold28V
UVETHRES(PVDDPVDD under voltage error threshold4.2V
OTETHRESOver temperature error threshold160°C
OTEHystersisOver temperature error hysteresis10°C
OTWTHRESOver temperature warning level 1Read by register 0x73 bit0112°C
OTWTHRESOver temperature warning level 2Read by register 0x73 bit1122°C
OTWTHRESOver temperature warning level 3Read by register 0x73 bit2134°C
OTWTHRESOver temperature warning level 4Read by register 0x73 bit3146°C
Speaker Amplifier (Stereo BTL)
|VOS|Amplifier offset voltageMeasured differentially with zero input data, programmable gain configured with 29.5 VP gain, VPVDD = 16 V–7.57.5mV
PO(SPK)Output Power (Per Channel)VPVDD = 14.4 V, SPK_GAIN = 29.5 VP, RSPK = 6 Ω, f = 1 kHz THD+N = 10%17.8W
VPVDD = 14.4 V, SPK_GAIN = 29.5 VP, RSPK = 6 Ω, f = 1 kHz THD+N = 1%14.5W
VPVDD = 24 V, SPK_GAIN = 29.5 VP, RSPK = 8 Ω, f = 1 kHz THD+N = 10% (Instantaneous Output Power)38W
VPVDD = 24 V, SPK_GAIN = 29.5 VP, RSPK = 8 Ω, f = 1 kHz THD+N = 1% (Continuous Output Power)30W
THD+NSPKTotal harmonic distortion and noise
(PO = 1 W, f = 1 kHz, RSPK = 6 Ω)		VPVDD = 12 V, SPK_GAIN = 20.9 VP LC-filter0.03%
VPVDD = 24 V, SPK_GAIN = 29.5 VP, LC-filter0.03%
ICN(SPK)Idle channel noise (A-weighted, AES17)VPVDD = 12 V, LC-filter, Load = 6 Ω, Hybrid Modulation32µVrms
ICN(SPK)VPVDD = 12 V, LC-filter, Load = 6 Ω, BD Modulation40
ICN(SPK)VPVDD = 24 V, LC-filter ,Load = 6 Ω, Hybrid Modulation35
ICN(SPK)VPVDD = 24 V, LC-filter ,Load = 6 Ω, BD Modulation45
DRDynamic rangeA-Weighted, -60 dBFS method. PVDD = 24 V, SPK_GAIN = 29.5 Vp111dB
SNRSignal-to-noise ratioA-Weighted, referenced to 1% THD+N Output Level, PVDD = 24 V111dB
A-Weighted, referenced to 1% THD+N Output Level, PVDD = 14.4 V108dB
KSVRPower supply rejection ratioInjected Noise = 1 kHz, 1 Vrms, PVDD = 14.4 V, input audio signal = digital zero72dB
CrosstalkSPKCrosstalk (worst case between left-to-right and right-to-left coupling)f = 1 kHz-100dB
Speaker Amplifier (Mono PBTL)
PO(SPK)Output PowerVPVDD = 19 V, SPK_GAIN = 29.5 VP, RSPK = 3 Ω, f = 1 kHz, THD+N = 1%50W
VPVDD = 19 V, SPK_GAIN = 29.5 VP, RSPK = 3 Ω, f = 1 kHz, THD+N = 10%60W
VPVDD = 22 V, SPK_GAIN = 29.5 VP, RSPK = 4 Ω, f = 1 kHz, THD+N = 1%53W
VPVDD = 22 V, SPK_GAIN = 29.5 VP, RSPK = 4 Ω, f = 1 kHz, THD+N = 10%65W
THD+NSPKTotal harmonic distortion and noise
(PO = 1 W, f = 1 kHz		VPVDD = 19 V, SPK_GAIN = 20.9 Vp, LC-filter RSPK = 3 Ω)0.03%
VPVDD = 24 V, SPK_GAIN = 29.5 VP, LC-filter RSPK = 4 Ω)0.03%
DRDynamic rangeA-Weighted, -60 dBFS method, PVDD=19V109dB
SNRSignal-to-noise ratioA-Weighted, referenced to 1% THD+N Output Level, PVDD = 19 V109dB
A-Weighted, referenced to 1% THD+N Output Level, PVDD = 24 V111dB