JAJSI51A May   2019  – January 2023 TAS5825P

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
      2. 7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
      3. 7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      4. 7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port – Clock Rates
      4. 9.3.4 Clock Halt Auto-Recovery
      5. 9.3.5 Sample Rate on the Fly Change
      6. 9.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 9.3.7 Digital Audio Processing
      8. 9.3.8 Class-D Audio Amplifier
        1. 9.3.8.1 Speaker Amplifier Gain Select
        2. 9.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Software Control
      2. 9.4.2 Speaker Amplifier Operating Modes
        1. 9.4.2.1 BTL Mode
        2. 9.4.2.2 PBTL Mode
      3. 9.4.3 Low EMI Modes
        1. 9.4.3.1 Spread Spectrum
        2. 9.4.3.2 Channel to Channel Phase Shift
        3. 9.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 9.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 9.4.3.3.2 Phase Synchronization With GPIO
      4. 9.4.4 Thermal Foldback
      5. 9.4.5 Device State Control
      6. 9.4.6 Device Modulation
        1. 9.4.6.1 BD Modulation
        2. 9.4.6.2 1SPW Modulation
        3. 9.4.6.3 Hybrid Modulation
    5. 9.5 Programming and Control
      1. 9.5.1 I2 C Serial Communication Bus
      2. 9.5.2 I2 C Peripheral Address
        1. 9.5.2.1 Random Write
        2. 9.5.2.2 Sequential Write
        3. 9.5.2.3 Random Read
        4. 9.5.2.4 Sequential Read
        5. 9.5.2.5 DSP Memory Book, Page and BQ update
        6. 9.5.2.6 Checksum
          1. 9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 9.5.2.6.2 Exclusive or (XOR) Checksum
      3. 9.5.3 Control via Software
        1. 9.5.3.1 Startup Procedures
        2. 9.5.3.2 Shutdown Procedures
        3. 9.5.3.3 Protection and Monitoring
          1. 9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 9.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 9.5.3.3.3 DC Detect
    6. 9.6 Register Maps
      1. 9.6.1 CONTROL PORT Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Bootstrap Capacitors
      2. 10.1.2 Inductor Selections
      3. 10.1.3 Power Supply Decoupling
      4. 10.1.4 Output EMI Filtering
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
      2. 10.2.2 79
      3. 10.2.3 Design Requirements
      4. 10.2.4 Detailed Design procedures
        1. 10.2.4.1 Step One: Hardware Integration
        2. 10.2.4.2 Step Two: Hardware Integration
        3. 10.2.4.3 Step Three: Software Integration
      5. 10.2.5 Application Curves
      6. 10.2.6 MONO (PBTL) Systems
      7. 10.2.7 Application Curves
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 DVDD Supply
      2. 10.3.2 PVDD Supply
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 General Guidelines for Audio Amplifiers
        2. 10.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 10.4.1.3 Optimizing Thermal Performance
          1. 10.4.1.3.1 Device, Copper, and Component Layout
          2. 10.4.1.3.2 Stencil Pattern
            1. 10.4.1.3.2.1 PCB footprint and Via Arrangement
            2. 10.4.1.3.2.2 Solder Stencil
      2. 10.4.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Development Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation

Free-air room temperature 25°C (unless otherwise noted) Measurements were made using TAS5825PEVM board and Audio Precision System 2722 with Analog Analyzer filter set to 20-kHz brickwall filter. All measurements taken with audio frequency set to 1 kHz and device PWM frequency set to 768 kHz, the LC filter used was 4.7 μH / 0.68 μF （Pre-Filter PBTL, the merging of the two output channels in this device can be done before the inductor portion of the output filter, see details in GUID-9C07FBD7-D5CF-444A-9F0D-6673351C6811.html#GUID-9C07FBD7-D5CF-444A-9F0D-6673351C6811）, unless otherwise noted.

GUID-63A90F84-8289-4B3B-8F53-ADD663DE0596-low.gif
BD Modulation PO = 1W,2.5W,5W
FSW = 768 kHz Load = 3 Ω PBTL Mode
Figure 7-72 THD+N vs Frequency-PBTL
GUID-69A41ECF-21CB-4260-9179-8E60F0193E04-low.gif
BD Modulation PO = 1W,2.5W,5W
FSW = 768 kHz Load = 3 Ω PBTL Mode
Figure 7-74 THD+N vs Frequency-PBTL
GUID-A76534F5-A66F-4589-A07F-5E0AF41F86EC-low.gif
BD Modulation PO = 1W,2.5W,5W
FSW = 768 kHz Load = 3 Ω PBTL Mode
Figure 7-76 THD+N vs Frequency-PBTL
GUID-129A674D-95AE-48EF-A48F-CB29FFD61102-low.gif
BD Modulation
FSW = 768 kHz Load = 3 Ω, 4 Ω PBTL Mode
Figure 7-78 THD+N vs Output Power-PBTL
GUID-F634FD30-7E24-4957-887C-488A060AA61F-low.gif
BD Modulation
FSW = 768 kHz Load = 3 Ω, 4 Ω PBTL Mode
Figure 7-80 THD+N vs Output Power-PBTL
GUID-2D36244C-AC0E-4C8F-9CFB-50A60D64F896-low.gif
BD Modulation
FSW = 768 kHz Load = 4 Ω PBTL Mode
Figure 7-82 Output Power vs Supply Voltage
GUID-E6C27E20-D965-4676-A15D-97DDC15793C6-low.gif
BD Modulation
FSW = 768 kHzLoad = 3 Ω, PBTL
5 V EVM Battery with default PPC3 setting (-5.5 dB AGAIN)
Figure 7-84 Efficiency vs Output Power
GUID-2ED007A1-4D60-40F1-B514-5B4516CCA2B6-low.gif
BD Modulation
FSW = 384 kHz Load=4Ω, PBTL 5 V Battery Input approximately 5 V – 16 V Boost Default PPC3 Setting (-5.5 dB AGAIN)
Figure 7-86 EVM Efficiency Comparison ON/OFF Hybrid-Pro
GUID-73ABE337-52CC-4BFE-9B41-5BDB3DE6279F-low.gif
BD Modulation PO = 1W,2.5W,5W
FSW = 768 kHz Load = 4 Ω PBTL Mode
Figure 7-73 THD+N vs Frequency-PBTL
GUID-091A99AD-2903-4D35-AE0C-63F54DB5259E-low.gif
BD Modulation PO = 1W,2.5W,5W
FSW = 768 kHz Load = 4 Ω PBTL Mode
Figure 7-75 THD+N vs Frequency-PBTL
GUID-F1F02BEB-FB0C-444D-B119-1AB3F7137938-low.gif
BD Modulation PO = 1W,2.5W,5W
FSW = 768 kHz Load = 4 Ω PBTL Mode
Figure 7-77 THD+N vs Frequency-PBTL
GUID-2D237A5D-657B-40B2-B1D2-D9451982D7E1-low.gif
BD Modulation
FSW = 768 kHz Load = 3 Ω, 4 Ω PBTL Mode
Figure 7-79 THD+N vs Output Power-PBTL
GUID-69D8B417-48F9-4F98-AB18-24FAE3DDF5CE-low.gif
BD Modulation
FSW = 768 kHz Load = 3 Ω PBTL Mode
Figure 7-81 Output Power vs Supply Voltage
GUID-A2E88AB5-0FD4-4CE0-A3C4-A8AD80DC1789-low.gif
BD Modulation
FSW = 768 kHz Load = 3 Ω PBTL Mode
Figure 7-83 Efficiency vs Output Power
GUID-975B2406-D425-4E98-960F-CAAB2772922C-low.gif
BD Modulation
FSW = 384 kHz Load=3Ω, PBTL 5 V Battery Input approximately 5 V – 16 V Boost Default PPC3 Setting (-5.5 dB AGAIN)
Figure 7-85 EVM Efficiency Comparison ON/OFF Hybrid-Pro
GUID-030F1043-A116-4DD8-8968-D061F0A60878-low.gif
BD Modulation
FSW = 768 kHz Load =4Ω PBTL Mode
Figure 7-87 Idle Channel Noise vs Supply Voltage