JAJSM72A June   2021  – December 2021 TAS5828M

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 6.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 6.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 6.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Device Clocking
      3. 8.3.3 Serial Audio Port – Clock Rates
      4. 8.3.4 Clock Halt Auto-recovery
      5. 8.3.5 Sample Rate on the Fly Change
      6. 8.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 8.3.7 Digital Audio Processing
      8. 8.3.8 Class D Audio Amplifier
        1. 8.3.8.1 Speaker Amplifier Gain Select
        2. 8.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Software Control
      2. 8.4.2 Speaker Amplifier Operating Modes
        1. 8.4.2.1 BTL Mode
        2. 8.4.2.2 PBTL Mode
      3. 8.4.3 Low EMI Modes
        1. 8.4.3.1 Spread Spectrum
        2. 8.4.3.2 Channel to Channel Phase Shift
        3. 8.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 8.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 8.4.3.3.2 Phase Synchronization With GPIO
      4. 8.4.4 Thermal Foldback
      5. 8.4.5 Device State Control
      6. 8.4.6 Device Modulation
        1. 8.4.6.1 BD Modulation
        2. 8.4.6.2 1SPW Modulation
        3. 8.4.6.3 Hybrid Modulation
    5. 8.5 Programming and Control
      1. 8.5.1 I2 C Serial Communication Bus
      2. 8.5.2 Hardware Control Mode
      3. 8.5.3 I2 C Target Address
        1. 8.5.3.1 Random Write
        2. 8.5.3.2 Sequential Write
        3. 8.5.3.3 Random Read
        4. 8.5.3.4 Sequential Read
        5. 8.5.3.5 DSP Memory Book, Page and BQ update
        6. 8.5.3.6 Checksum
          1. 8.5.3.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 8.5.3.6.2 Exclusive or (XOR) Checksum
      4. 8.5.4 Control via Software
        1. 8.5.4.1 Startup Procedures
        2. 8.5.4.2 Shutdown Procedures
      5. 8.5.5 Protection and Monitoring
        1. 8.5.5.1 Overcurrent Limit (Cycle-By-Cycle)
        2. 8.5.5.2 Overcurrent Shutdown (OCSD)
        3. 8.5.5.3 DC Detect Error
        4. 8.5.5.4 Overtemperature Shutdown (OTSD)
        5. 8.5.5.5 PVDD Overvoltage and Undervoltage Error
        6. 8.5.5.6 PVDD Drop Detection
        7. 8.5.5.7 Clock Fault
    6. 8.6 Register Maps
      1. 8.6.1 CONTROL PORT Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Inductor Selections
      2. 9.1.2 Bootstrap Capacitors
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design procedures
        1. 9.2.3.1 Step One: Hardware Integration
        2. 9.2.3.2 Step Two: Hardware Integration
        3. 9.2.3.3 Step Three: Software Integration
      4. 9.2.4 MONO (PBTL) Systems
      5. 9.2.5 Advanced 2.1 System (Two TAS5828M Devices)
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
          2. 11.1.3.2.2 Solder Stencil
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DAD|32
サーマルパッド・メカニカル・データ
発注情報

8.4.3.2 Channel to Channel Phase Shift

This device supports channel to channel 180-degree PWM phase shift to minimize the EMI. Bit 0 of Register 0x53 can be used to disable or enable the phase shift.