JAJSM72A June 2021 – December 2021 TAS5828M
PRODUCTION DATA
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The TAS5828M devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio Interface.
Figure 8-1 shows the basic data flow and clock Distribution.
The Serial Audio Interface typically has 3 connection pins which are listed as follows:
The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP and the DAC clock.
The TAS5828M device has an audio sampling rate detection circuit that automatically senses which frequency the sampling rate is operating. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96 kHz, 176.4 kHz – 192 kHz are supported. The sampling frequency detector sets the clock for DAC and DSP automatically.
If the input LRCLK/SCLK stopped during music playing, the TAS5828M DSP switches to sleep state and waiting for the clock recovery (Class D output switches to Hiz automatically ), once LRCLK/SCLK recovered, TAS5828M auto recovers to the play mode. There is no need to reload the DSP code.