JAJSM72A June   2021  – December 2021 TAS5828M

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 6.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 6.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 6.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Device Clocking
      3. 8.3.3 Serial Audio Port – Clock Rates
      4. 8.3.4 Clock Halt Auto-recovery
      5. 8.3.5 Sample Rate on the Fly Change
      6. 8.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 8.3.7 Digital Audio Processing
      8. 8.3.8 Class D Audio Amplifier
        1. 8.3.8.1 Speaker Amplifier Gain Select
        2. 8.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Software Control
      2. 8.4.2 Speaker Amplifier Operating Modes
        1. 8.4.2.1 BTL Mode
        2. 8.4.2.2 PBTL Mode
      3. 8.4.3 Low EMI Modes
        1. 8.4.3.1 Spread Spectrum
        2. 8.4.3.2 Channel to Channel Phase Shift
        3. 8.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 8.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 8.4.3.3.2 Phase Synchronization With GPIO
      4. 8.4.4 Thermal Foldback
      5. 8.4.5 Device State Control
      6. 8.4.6 Device Modulation
        1. 8.4.6.1 BD Modulation
        2. 8.4.6.2 1SPW Modulation
        3. 8.4.6.3 Hybrid Modulation
    5. 8.5 Programming and Control
      1. 8.5.1 I2 C Serial Communication Bus
      2. 8.5.2 Hardware Control Mode
      3. 8.5.3 I2 C Target Address
        1. 8.5.3.1 Random Write
        2. 8.5.3.2 Sequential Write
        3. 8.5.3.3 Random Read
        4. 8.5.3.4 Sequential Read
        5. 8.5.3.5 DSP Memory Book, Page and BQ update
        6. 8.5.3.6 Checksum
          1. 8.5.3.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 8.5.3.6.2 Exclusive or (XOR) Checksum
      4. 8.5.4 Control via Software
        1. 8.5.4.1 Startup Procedures
        2. 8.5.4.2 Shutdown Procedures
      5. 8.5.5 Protection and Monitoring
        1. 8.5.5.1 Overcurrent Limit (Cycle-By-Cycle)
        2. 8.5.5.2 Overcurrent Shutdown (OCSD)
        3. 8.5.5.3 DC Detect Error
        4. 8.5.5.4 Overtemperature Shutdown (OTSD)
        5. 8.5.5.5 PVDD Overvoltage and Undervoltage Error
        6. 8.5.5.6 PVDD Drop Detection
        7. 8.5.5.7 Clock Fault
    6. 8.6 Register Maps
      1. 8.6.1 CONTROL PORT Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Inductor Selections
      2. 9.1.2 Bootstrap Capacitors
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design procedures
        1. 9.2.3.1 Step One: Hardware Integration
        2. 9.2.3.2 Step Two: Hardware Integration
        3. 9.2.3.3 Step Three: Software Integration
      4. 9.2.4 MONO (PBTL) Systems
      5. 9.2.5 Advanced 2.1 System (Two TAS5828M Devices)
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
          2. 11.1.3.2.2 Solder Stencil
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

6.5 Electrical Characteristics

Free-air room temperature 25°C, 1SPW Mode, LC filter=10uH+0.68uF, Fsw=384kHz, Class D Bandwidth=80kHz, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital I/O
|IIH| Input logic high current level
for DVDD referenced digital
input pins		 VIN(DigIn) = VDVDD 10 uA
|IIL| Input logic low current level
for DVDD referenced digital
input pins		 VIN(DigIn) = 0 V –10 uA
VIH(Digin) Input logic high threshold for
DVDD referenced digital
inputs		 70% VDVDD
VIL(Digin) Input logic low threshold for
DVDD referenced digital
inputs		 30% VDVDD
VOH(Digin) Output logic high voltage
level		 IOH = 4 mA 80% VDVDD
VOL(Digin) Output logic low voltage level IOH = –4 mA 20% VDVDD
I2C CONTROL PORT
CL(I2C) Allowable load capacitance
for each I2C Line		 400 pF
fSCL(fast) Support SCL frequency No wait states, fast mode 400 kHz
fSCL(slow) Support SCL frequency No wait states, slow mode 100 kHz
SERIAL AUDIO PORT
tDLY Required LRCLK/FS to SCLK
rising edge delay		 5 ns
DSCLK Allowable SCLK duty cycle 40% 60%
fS Supported input sample rates 32 192 kHz
fSCLK Supported SCLK frequencies 32 64 fS
fSCLK SCLK frequency 24.576 MHz
AMPLIFIER OPERATING MODE AND DC PRAMETERS
ICC Quiescent supply current of
DVDD		 PDN = 2 V, DVDD = 3.3 V, Play mode,
General Audio Process flow with full DSP running		 23 mA
ICC Quiescent supply current of
DVDD		 PDN = 2 V, DVDD = 3.3 V,Sleep mode 1 mA
ICC Quiescent supply current of
DVDD		 PDN = 2 V, DVDD = 3.3 V,Deep Sleep mode 1 mA
ICC Quiescent supply current of
DVDD		 PDN = 0.8 V, DVDD = 3.3 V,Shutdown mode 16 uA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, 1SPW Modulation, Play Mode		 39 mA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Output Hiz Mode		 11 mA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Sleep Mode		 7.5 mA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Deep Sleep Mode		 10 uA
ICC Quiescent supply current of
PVDD		 PDN = 2 V, PVDD = 18 V, No Load, LC filter =
10 μH + 0.68 μF, FSW = 384 kHz, Shutdown Mode		 10 uA
AV(SPK_AMP) Programmable Gain Value represents the "peak voltage" disregarding
clipping due to lower PVDD
Measured at 0 dB input(1FS)		 13.75 29.4 dBV
ΔAV(SPK_AMP) Amplifier gain error Gain = 26.4dBV 0.5 dB
fSPK_AMP Switching frequency of the
speaker amplifier. 		 Software Mode 384 kHz
480 kHz
768 kHz
Hardware Mode 480 kHz
768 kHz
RDS(on) Drain-to-source on resistance
of the individual output
MOSFETs		 FET + Metallization. VPVDD=24V, I(OUT)=500mA,
TJ=25℃		 90 mΩ
PROTECTION
OCETHRES Over-Current Error Threshold
(Speaker current)		 Speaker Output Current (Post LC filter), Speaker
current, LC Filter=10uH+0.68uF, BTL Mode		 7.5 8 8.5 A
UVETHRES(PVDD) PVDD under voltage error
threshold		 3.7 4 4.2 V
OVETHRES(PVDD) PVDD over voltage error
threshold		 27 28.1 29.2 V
DCETHRES Output DC Error protection
threshold		 Class D Amplifier's output DC voltage cross
speaker load to trigger Output DC Fault protection		 1.7 V
TDCDET Output DC Detect time Class D Amplifier's output remain at or above
DCETHRES		 570 ms
OTETHRES Over temperature error
threshold		 165 ℃
OTEHystersis Over temperature error
hysteresis		 10 ℃
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit0 112 °C
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit1 122 °C
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit2 134 °C
OTWTHRES Over temperature warning
level		 Read by register 0x73 bit3 146 °C
AUDIO PERFORMACNE (STEREO BTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data,
programmable gain configured with 29.4dBV
analog gain, VPVDD range:12V~24V		 –5 5 mV
PO(SPK) Output Power (Per Channel) VPVDD = 18 V, LC Filter=10uH+0.68uF, RSPK = 4 Ω, f = 1 KHz, THD+N =
10%		 43 W
VPVDD = 18 V, LC Filter=10uH+0.68uF, RSPK = 4 Ω, f = 1 KHz, THD+N =
1%		 35 W
VPVDD = 18 V, LC Filter=10uH+0.68uF, RSPK = 6 Ω, f = 1 KHz, THD+N =
10%		 31 W
VPVDD = 18 V, LC Filter=10uH+0.68uF, RSPK = 6 Ω, f = 1 KHz, THD+N =
1%		 25 W
VPVDD = 21 V, LC Filter=10uH+0.68uF, RSPK = 4 Ω, f = 1 KHz, THD+N =
10%		 55 W
VPVDD = 21 V, LC Filter=10uH+0.68uF, RSPK = 4 Ω, f = 1 KHz, THD+N =
1%		 44 W
VPVDD = 24 V, LC Filter=10uH+0.68uF, RSPK = 6 Ω, f = 1 KHz, THD+N =
10%		 54 W
VPVDD = 24 V, LC Filter=10uH+0.68uF, RSPK = 6 Ω, f = 1 KHz, THD+N =
1%		 43 W
THD+NSPK Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz)		 VPVDD = 18 V,LC Filter=10uH+0.68uF, Load=4Ω 0.08 %
VPVDD = 24 V,LC Filter=10uH+0.68uF,Load=6Ω 0.06 %
ICN(SPK) Idle channel noise(Aweighted,
AES17)		 VPVDD = 18 V, LC Filter=10uH+0.68uF, Load=4 Ω, Fsw=768kHz, BD Modulation 40 µVrms
VPVDD = 18 V, LC Filter=10uH+0.68uF,Load=4 Ω, Fsw=384kHz, 1SPW Modulation 35 µVrms
VPVDD = 24 V, LC Filter=10uH+0.68uF,,Load=6 Ω, Fsw=768kHz, BD Modulation 35 µVrms
VPVDD = 24 V, LC Filter=10uH+0.68uF,Load=6 Ω, Fsw=384kHz, 1SPW Modulation 35 µVrms
DR Dynamic range A-Weighted, -60 dBFS method. VPVDD = 24 V,Load=6Ω
Analog Gain = 29.4dBV		 111 dB
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=24V, load=6Ω		 111 dB
A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=18V, Load=4Ω		 106 dB
PSRR Power supply rejection ratio Injected Noise = 1 KHz, 1 Vrms, VPVDD = 24 V,
input audio signal = digital zero		 72 dB
X-talkSPK Cross-talk (worst case
between left-to-right and
right-to-left coupling)		 f = 1 KHz, based on Inductor (DFEG7030D-4R7)
from Murata		 100 dB
AUDIO PERFORMANCE (MONO PBTL)
|VOS| Amplifier offset voltage Measured differentially with zero input data,
programmable gain configured with 29.4dBV
Analog gain, VPVDD = 12V-24V range,  1SPW mode		 –5 5 mV
PO(SPK) Output Power VPVDD = 24 V, RSPK = 3 Ω, f = 1KHz, THD+N =
1%		 84 W
VPVDD = 24 V, RSPK = 3 Ω, f = 1KHz, THD+N =
10%		 104 W
VPVDD = 18 V, RSPK = 2 Ω, f = 1KHz, THD+N =
1%		 67 W
VPVDD = 18 V, RSPK = 2 Ω, f = 1KHz, THD+N =
10%		 80 W
THD+NSPK Total harmonic distortion and
noise
(PO = 1 W, f = 1 KHz)		 VPVDD = 18 V, LC-filter=10uH+0.68uF, RSPK = 2 Ω 0.07 %
VPVDD = 24 V, LC-filter=10uH+0.68uF, RSPK = 3 Ω 0.05 %
DR Dynamic range A-Weighted, -60 dBFS method, VPVDD=24V, RSPK
= 3 Ω.		 111 dB
SNR Signal-to-noise ratio A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=24V, RSPK = 3 Ω		 108 dB
A-Weighted,referenced to 1% THD+N Output
Level, VPVDD=18V, RSPK = 2 Ω		 106 dB
PSRR Power supply rejection ratio Injected Noise = 1 KHz, 1 Vrms,VPVDD = 18 V,
input audio signal = digital zero		 72 dB