JAJSKD3 november 2020 TAS6424MS-Q1
PRODUCTION DATA
The device supports MCLK rates of 128 × fS, 256 × fS, or 512 × fS.
The device supports SCLK rates of 32 × fS or 64 × fS in I2S, LJ or RJ modes or 128 × fS, or 256 × fS in TDM mode.
The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz.
The maximum clock frequency is 25 MHz. Therefore, for a 96 kHz FSYNC rate, the maximum MCLK rate is
256 × fS.
Duty cycle of 50% is required for 128x FSYNC, for 256x and 512x 50% duty cycle is not required.