JAJSKD3 november 2020 TAS6424MS-Q1
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AREF | 4 | PWR | VREG and VCOM bypass capacitor return |
AVDD | 8 | PWR | Voltage regulator bypass. Connect 1 µF capacitor from AVDD to AVSS |
AVSS | 7 | PWR | AVDD bypass capacitor return |
BST_1M | 31 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_1P | 35 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_2M | 37 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_2P | 41 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_3M | 44 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_3P | 48 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_4M | 50 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_4P | 54 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
FAULT | 26 | DO | Reports a fault (active low, open drain), 100-kΩ internal pull-up resistor |
FSYNC | 14 | DI | Audio frame clock input |
GND | 1, 11, 17, 18, 28, 33, 36, 39, 46, 49, 52 | GND | Ground |
GVDD | 9 | PWR | Gate drive voltage regulator derived from VBAT input pin. Connect 2.2 µF capacitor to GND |
10 | Gate drive voltage regulator derived from VBAT input pin. Connect 2.2 µF capacitor to GND | ||
I2C_ADDR0 | 22 | DI | I2C address pins. Refer to Table 9-8 |
I2C_ADDR1 | 23 | ||
MCLK | 12 | DI | Audio master clock input |
MUTE | 25 | DI | Mutes the device outputs (active low) while keeping output FETs switching at 50%, 100-kΩ internal pull-down resistor |
OUT_1M | 32 | NO | Negative output for the channel |
OUT_1P | 34 | PO | Positive output for the channel |
OUT_2M | 38 | NO | Negative output for the channel |
OUT_2P | 40 | PO | Positive output for the channel |
OUT_3M | 45 | NO | Negative output for the channel |
OUT_3P | 47 | PO | Positive output for the channel |
OUT_4M | 51 | NO | Negative output for the channel |
OUT_4P | 53 | PO | Positive output for the channel |
PVDD | 2, 29, 30, 42, 43, 55, 56 | PWR | PVDD voltage input (can be connected to battery). Bulk capacitor and bypass capacitor required |
SCL | 20 | DI | I2C clock input |
SCLK | 13 | DI | Audio bit and serial clock input |
SDA | 21 | DI/O | I2C data input and output |
SDIN1 | 15 | DI | TDM data input and audio I2S data input for channels 1 and 2 |
SDIN2 | 16 | DI | Audio I2S data input for channels 3 and 4 |
STANDBY | 24 | DI | Enables low power standby state (active Low), 100-kΩ internal pull-down resistor |
VBAT | 3 | PWR | Battery voltage input |
VCOM | 6 | PWR | Bias voltage |
VDD | 19 | PWR | 3.3 V external supply voltage |
VREG | 5 | PWR | Voltage regulator bypass |
WARN | 27 | DO | Clip and overtemperature warning (active low, open drain), 100-kΩ internal pull-up resistor |
Thermal Pad | — | GND | Provides both electrical and thermal connection for the device. Heatsink must be connected to GND. |