JAJSKD3 november 2020 TAS6424MS-Q1
PRODUCTION DATA
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
PVDD | Output FET Supply Voltage Range | Relative to GND | 4.5 | 18 | V | |
VBAT | Battery Supply Voltage Input | Relative to GND | 4.5 | 14.4 | 18 | |
VDD | DC Logic supply | Relative to GND | 3.0 | 3.3 | 3.5 | |
TA | Ambient temperature | –40 | 125 | °C | ||
TJ | Junction temperature | An adequate thermal design is required | –40 | 150 | ||
RL | Minimum speaker load impedance | BTL Mode | 2 | 4 | Ω | |
PBTL Mode | 1 | 2 | ||||
RPU_I2C | I2C pullup resistance on SDA and SCL pins | 1 | 4.7 | 10 | kΩ | |
CBypass | External capacitance on bypass pins | Pin 2, 3, 5, 6, 8, 19 | 1 | µF | ||
CGVDD | External capacitance on GVDD pins | Pin 9, 10 | 2.2 | µF | ||
COUT | External capacitance to GND on OUT pins | Limit set by DC-diagnostic timing | 1 | 3.3 | µF | |
LO | Output filter inductance | Minimum inductance at ISD current levels |
1 | µH |