JAJSR70A December 2022 – September 2023 TAS6424R-Q1
PRODUCTION DATA
The Channel Faults (overcurrent, DC detection) register is shown in Figure 9-27 and described in Table 9-23.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1 OC | CH2 OC | CH3 OC | CH4 OC | CH1 DC | CH2 DC | CH3 DC | CH4 DC |
R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH1 OC | R | 0 | 0: No overcurrent fault detected 1: Overcurrent fault detected |
6 | CH2 OC | R | 0 | 0: No overcurrent fault detected 1: Overcurrent fault detected |
5 | CH3 OC | R | 0 | 0: No overcurrent fault detected 1: Overcurrent fault detected |
4 | CH4 OC | R | 0 | 0: No overcurrent fault detected 1: Overcurrent fault detected |
3 | CH1 DC | R | 0 | 0: No DC fault detected 1: DC fault detected |
2 | CH2 DC | R | 0 | 0: No DC fault detected 1: DC fault detected |
1 | CH3 DC | R | 0 | 0: No DC fault detected 1: DC fault detected |
0 | CH4 DC | R | 0 | 0: No DC fault detected 1: DC fault detected |