JAJSR70A December   2022  – September 2023 TAS6424R-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Options
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 ESD Ratings
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics: Bridge-Tied Load (BTL)
    7. 7.7 Typical Characteristics: Bridge-Tied Load (BTL, 384 kHz)
    8. 7.8 Typical Characteristics: Parallel Bridge-Tied (PBTL)
    9. 7.9 Typical Characteristics: Parallel Bridge-Tied Load (PBTL, 384 kHz)
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Audio Port
        1. 9.3.1.1 I2S Mode
        2. 9.3.1.2 Left-Justified Timing
        3. 9.3.1.3 Right-Justified Timing
        4. 9.3.1.4 TDM Mode
        5. 9.3.1.5 Supported Clock Rates
        6. 9.3.1.6 Audio-Clock Error Handling
      2. 9.3.2  DC Blocking
      3. 9.3.3  Volume Control and Gain
      4. 9.3.4  High-Frequency Pulse-Width Modulator (PWM)
      5. 9.3.5  EMI Management Features
        1. 9.3.5.1 Spread-Spectrum
        2. 9.3.5.2 Channel-to-Channel Output Phase Control
      6. 9.3.6  Gate Drive
      7. 9.3.7  Power FETs
      8. 9.3.8  Load Diagnostics
        1. 9.3.8.1 DC Load Diagnostics
        2. 9.3.8.2 Line Output Diagnostics
        3. 9.3.8.3 AC Load Diagnostics
          1. 9.3.8.3.1 Impedance Magnitude Measurement
          2. 9.3.8.3.2 Impedance Phase Reference Measurement
          3. 9.3.8.3.3 Impedance Phase Measurement
      9. 9.3.9  Protection and Monitoring
        1. 9.3.9.1 Overcurrent Limit (ILIMIT)
        2. 9.3.9.2 Overcurrent Shutdown (ISD)
        3. 9.3.9.3 DC Detect
        4. 9.3.9.4 Clip Detect
        5. 9.3.9.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 9.3.9.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 9.3.9.7 Undervoltage (UV) and Power-On-Reset (POR)
        8. 9.3.9.8 Overvoltage (OV) and Load Dump
      10. 9.3.10 Power Supply
        1. 9.3.10.1 Vehicle-Battery Power-Supply Sequence
          1. 9.3.10.1.1 Power-Up Sequence
          2. 9.3.10.1.2 Power-Down Sequence
        2. 9.3.10.2 Boosted Power-Supply Sequence
      11. 9.3.11 Hardware Control Pins
        1. 9.3.11.1 FAULT
        2. 9.3.11.2 WARN
        3. 9.3.11.3 MUTE
        4. 9.3.11.4 STANDBY
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes and Faults
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Communication Bus
      2. 9.5.2 I2C Bus Protocol
      3. 9.5.3 Random Write
      4. 9.5.4 Sequential Write
      5. 9.5.5 Random Read
      6. 9.5.6 Sequential Read
    6. 9.6 Register Maps
      1. 9.6.1  Mode Control Register (address = 0x00) [default = 0x00]
      2. 9.6.2  Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
      3. 9.6.3  Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
      4. 9.6.4  SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
      5. 9.6.5  Channel State Control Register (address = 0x04) [default = 0x55]
      6. 9.6.6  Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
      7. 9.6.7  DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
      8. 9.6.8  DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
      9. 9.6.9  DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
      10. 9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
      11. 9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
      12. 9.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
      13. 9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
      14. 9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
      15. 9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
      16. 9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
      17. 9.6.17 Warnings Register (address = 0x13) [default = 0x20]
      18. 9.6.18 Pin Control Register (address = 0x14) [default = 0x00]
      19. 9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
      20. 9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
      21. 9.6.21 AC Load Diagnostic Impedance Report Ch1 through Ch4 Registers (address = 0x17–0x1A) [default = 0x00]
      22. 9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
      23. 9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
      24. 9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
      25. 9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
      26. 9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
      27. 9.6.27 Clip Control Register (address = 0x22) [default = 0x01]
      28. 9.6.28 Clip Window Register (address = 0x23) [default = 0x14]
      29. 9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
      30. 9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
      31. 9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
      32. 9.6.32 Miscellaneous Control 5 Register (address = 0x28) [default = 0x0A]
      33. 9.6.33 Spread-Spectrum Control 1 Register (address = 0x77) [default = 0x00]
      34. 9.6.34 Spread Spectrum Control 2 Register (address = 0x78) [default = 0x3F]
      35. 9.6.35 Spread Spectrum Control 3 Register (address = 0x79) [default = 0x00]
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 AM-Radio Band Avoidance
      2. 10.1.2 Parallel BTL Operation (PBTL)
      3. 10.1.3 Demodulation Filter Design
      4. 10.1.4 Line Driver Applications
    2. 10.2 Typical Application
      1. 10.2.1 BTL Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 Communication
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Hardware Design
          2. 10.2.1.2.2 Digital Input and the Serial Audio Port
          3. 10.2.1.2.3 Bootstrap Capacitors
          4. 10.2.1.2.4 Output Reconstruction Filter
      2. 10.2.2 PBTL Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
        1. 10.4.1.1 Electrical Connection of Thermal pad and Heat Sink
        2. 10.4.1.2 EMI Considerations
        3. 10.4.1.3 General Guidelines
      2. 10.4.2 Layout Example
      3. 10.4.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
    2. 12.2 Tape and Reel Information
    3. 12.3 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1.4 TDM Mode

TDM mode supports 4 or 8 channels of audio data. The TDM mode is automatically selected when the TDM clocks are present. The device can be configured through I2C to use different stereo pairs in the TDM data stream. The TDM mode supports 16-bit, 24-bit, and 32-bit input data lengths.

In TDM mode, SCLK must be 128 x fs or 256 x fs, depending on the TDM slot size. In TDM mode SCLK and MCLK can be connected together. If SCLK and MCLK are connected together or the frequency of SCLK and MCLK is equal, FSYNC must be a minimum 2 MCLK pulses long.

In TDM mode, the SDIN1 pin (pin 15) is used for digital audio data. TI recommends to connect the unused SDIN2 pin (pin 16) to ground.Table 9-1 lists register settings for the TDM channel selection.

Table 9-1 TDM Channel Selection
REGISTER SETTINGTDM8 CHANNEL SLOT
0x03
BIT 5		0x03
BIT 3		12345678
00CH1CH2CH3CH4————
10————CH1CH2CH3CH4
01CH3CH4CH1CH2————
11————CH3CH4CH1CH2

If PBTL mode is programmed for channel 1/2 or channel 3/4 the datasource can be set according to Table 9-2.

Table 9-2 TDM Channel Selection in PBTL Mode
REGISTER SETTINGTDM8 CHANNEL SLOT
0x03
BIT 5		0x03
BIT 3		0x21
BIT 6		12345678
000PBTL CH1/2—PBTL CH3/4—————
100————PBTL CH1/2—PBTL CH3/4—
001—PBTL CH1/2—PBTL CH3/4————
101—————PBTL CH1/2—PBTL CH3/4
010PBTL CH3/4—PBTL CH1/2—————
110————PBTL CH3/4—PBTL CH1/2—
011—PBTL CH3/4—PBTL CH1/2————
111—————PBTL CH3/4—PBTL CH1/2