JAJSNE4B December   2022  – November 2023 TCA39416

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Voltage Waveforms
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Architecture
      2. 7.3.2 Enable and Disable
      3. 7.3.3 Pull up resistors on I/O Lines
      4. 7.3.4 Input Driver Requirements
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

The TCA39416 device is a directionless voltage-level translator specifically designed for translating logic voltage levels. The device is MIPI I3C v1.1.1 compatible supporting data rates up to 12.5 Mbps in I3C Single Data Rate (SDR) mode and 25 Mbps in I3C High Data Rate (HDR-DDR) mode. Like SDR Mode, HDR-DDR Mode uses SCL as a clock; however unlike SDR, data is sampled on both edges of clock SCL effectively doubling the data rate achieving 25 Mbps.

The A and B ports are able to accept I/O voltages ranging from 0.72 V to 1.98 V. VCCA must be ≤ VCCB to ensure proper operation. The device is a pass-gate architecture with edge-rate accelerators (one-shots) to improve the overall data rate and supports both high speed push-pull and low speed open-drain operation.

MIPI I3C specification requires dynamic pull-up control to switch between “strong pull-up” and “weak pull-up” to optimize open-drain and push-pull timing requirements. In TCA39416, the internal 10-kΩ pull-up resistors on Ax and Bx pins are enabled based on respective VCC voltage and OE input and act as High-Keeper when the bus is high.

When OE is low, the TCA39416 is disabled, the one shots and internal pull ups are also disabled.