JAJSFZ3C January   2011  – August 2018 TCA4311A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rise-Time Accelerators
      2. 8.3.2 READY Digital Output
      3. 8.3.3 EN Low Current Disable
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up
      2. 8.4.2 Connection Circuitry
      3. 8.4.3 Missing ACK Event
        1. 8.4.3.1 System Impact
        2. 8.4.3.2 System Workaround
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Input to Output Offset Voltage
        2. 9.2.1.2 Propagation Delays
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Resistor Pull-Up Value Selection
      3. 9.2.3 Application Curves
      4. 9.2.4 Live Insertion and Capacitance Buffering CompactPCI Application
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
      5. 9.2.5 Live Insertion and Capacitance Buffering PCI Application
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
        3. 9.2.5.3 Application Curves
      6. 9.2.6 Repeater/Bus Extender Application
        1. 9.2.6.1 Design Requirements
        2. 9.2.6.2 Detailed Design Procedure
        3. 9.2.6.3 Application Curves
      7. 9.2.7 Systems With Disparate Supply Voltages
        1. 9.2.7.1 Design Requirements
        2. 9.2.7.2 Detailed Design Procedure
        3. 9.2.7.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.3.2 System Workaround

Changing the bus load on the master or slave side to either a larger value pull up resistor or adding bus capacitance can help to slow down the rise time accelerators from engaging. If adding capacitance, care should be taken to not overload the capacitance above the allowed limit specified by I2C standard.