JAJSHZ2C January   2014  – September 2019 TCA5013

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics—Power Supply and ESD
    6. 6.6  Electrical Characteristics—Card VCC
    7. 6.7  Electrical Characteristics—Card RST
    8. 6.8  Electrical Characteristics—Card CLK
    9. 6.9  Electrical Characteristics—Card Interface IO, C4 and C8
    10. 6.10 Electrical Characteristics—PRES
    11. 6.11 Electrical Characteristics—IOMC1 and IOMC2
    12. 6.12 Electrical Characteristics—CLKIN1 and CLKIN2
    13. 6.13 Electrical Characteristics—A0 and SHDN
    14. 6.14 Electrical Characteristics—INT
    15. 6.15 Electrical Characteristics—GPIO
    16. 6.16 Electrical Characteristics—SDA and SCL
    17. 6.17 Electrical Characteristics—Fault Condition Detection
    18. 6.18 I2C Interface Timing Requirements
    19. 6.19 I2C Interface Timing Characteristics
    20. 6.20 Synchronous Type 1 Card Activation Timing Characteristics
    21. 6.21 Synchronous Type 2 Card Activation Timing Characteristics
    22. 6.22 Card Deactivation Timing Characteristics
    23. 6.23 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Card Interface Modules
      2. 8.3.2 SAM Card Interface Modules
      3. 8.3.3 User Card Interface Module
      4. 8.3.4 Clock Division and Multiplexing
      5. 8.3.5 IO Multiplexing
      6. 8.3.6 GPIO Operation
      7. 8.3.7 Power Management Features
      8. 8.3.8 ESD Protection
      9. 8.3.9 I2C interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Off Mode
      2. 8.4.2  Shutdown Mode
      3. 8.4.3  Standby Mode
      4. 8.4.4  Active Mode
        1. 8.4.4.1 User Card Operating Mode Selection
        2. 8.4.4.2 Synchronous Type 1 Operating Mode
        3. 8.4.4.3 Synchronous Type 2 Operating Mode
        4. 8.4.4.4 Manual Operating Mode
        5. 8.4.4.5 Asynchronous Operating Mode
        6. 8.4.4.6 Warm Reset Sequence
        7. 8.4.4.7 Deactivation Sequence
      5. 8.4.5  User Card Insertion / Removal Detection
      6. 8.4.6  IO Operation
        1. 8.4.6.1 IO Switching Control
        2. 8.4.6.2 IO Rise Time and Fall Time control
        3. 8.4.6.3 Current Limiting on IO Pin
      7. 8.4.7  CLK Operation
        1. 8.4.7.1 CLK Switching
        2. 8.4.7.2 CLK Rise Time and Fall Time Control
        3. 8.4.7.3 Current Limiting On CLK Pin
      8. 8.4.8  RST Operation
        1. 8.4.8.1 Current Limiting On RST
      9. 8.4.9  Interrupt Operation
        1. 8.4.9.1  Card Insertion And Removal
        2. 8.4.9.2  Over Current Fault
        3. 8.4.9.3  Supervisor Fault
        4. 8.4.9.4  Over Temperature Fault
        5. 8.4.9.5  EARLY Fault
        6. 8.4.9.6  MUTE Fault
        7. 8.4.9.7  Synchronous Activation Complete
        8. 8.4.9.8  VCC Ramp Fault
        9. 8.4.9.9  GPIO Input State Transition
        10. 8.4.9.10 POR Interrupt
      10. 8.4.10 Power Management
        1. 8.4.10.1 Voltage Supervisor
        2. 8.4.10.2 DC-DC Boost
        3. 8.4.10.3 LDOs and Load Transient Response
    5. 8.5 Programming
      1. 8.5.1 I2C Interface Operation
        1. 8.5.1.1 I2C Read and Write Procedures
        2. 8.5.1.2 I2C Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Memory Map
        1. Table 12. 91
        2. Table 13. 92
        3. Table 14. 93
        4. Table 15. 94
        5. Table 16. 95
        6. Table 17. 96
        7. Table 18. 97
        8. Table 19. 98
        9. Table 20. 99
        10. Table 21. 100
        11. Table 22. 101
        12. Table 23. 102
        13. Table 24. 103
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IO Pin Fall Time Setting
        2. 9.2.2.2 CLK Pin Rise Time And Fall Time Settings
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On-Reset
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DC-DC Boost Layout Recommendation
      2. 11.1.2 Card Interface Layout Recommendations
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 商標
    2. 12.2 静電気放電に関する注意事項
    3. 12.3 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.5 User Card Insertion / Removal Detection

User card interface module in the TCA5013 has a PRES pin that is used to detect the presence of a card in that interface. In normal application the signal is connected to a switch that opens or closes when a card is inserted. Whenever a transition is seen on the PRES pin, the PRESL bit (Reg 0x00, bit 2) will be set and INT pin is asserted. Because this transition is associated with a mechanical switch, there is an internal debounce of ~20 ms before the PRESL bit is set and the INT is asserted. If the device sees a transition on the PRESL pin when the card interface is active, the device initiates a card deactivation sequence (see Deactivation Sequence). TCA5013 is capable of detecting card insertion even when it is in shutdown mode (see Shutdown Mode).

In addition to the PRESL_UC bit mentioned above, there is also a PRES_UC bit (Reg 0x00, bit 2), which indicates to the host whether or not a card is present in the user card slot. In order to accommodate different card cage topologies, the TCA5013 can be configured to detect card presence with a low to high or high to low, transition on the PRES pin. The CARD_DETECT_UC bit (Reg 0x01, bit 2) is used to configure the device for different card detection topologies. If CARD_DETECT_UC = 0 indicates to the TCA5013 that when a card is inserted in the slot, the PRES pin shall be low. CARD_DETECT_UC = 1 indicates to the host that when a card is inserted in the slot the PRES pin shall be high. The status of the PRES_UC bit is based on the status of the PRES pin and the CARD_DETECT_UC bit. The truth table in Table 1 shows the PRES_UC bit status based on the CARD_DETECT_UC bit and the PRES pin. When coming out of power off mode (see Power Off Mode) or shutdown mode (see Shutdown Mode) the CARD_DETECT_UC = 0. If there is a state transition on the PRES pin when the device is in shutdown mode, the INT pin asserted (after the 20 ms debounce).

Table 5. Truth Table Defining Status of PRES Bit

CARD DETECT BIT PRES PIN PRES BIT
0 0 1
0 1 0
1 0 0
1 1 1

Figure 9 to Figure 14 show timing waveforms of device power up and coming out of shutdown with and without a card inserted in the system. In below figures’ low to high PRES topology’ means that a high level on the PRES pin indicates a card is present. In below figures high to low PRES topology’ means that a low level on the PRES pin indicates a card is present. The below figures also show operation of INT pin and interrupt status register. For detailed description of the interrupt operation, refer to Interrupt Operation section.

TCA5013 fig013_SCPS253.gifFigure 9. Card detection in shutdown mode - Low to High PRES Topology
TCA5013 fig014_SCPS253.gifFigure 10. Card detection in shutdown mode - High to Low PRES Topology
TCA5013 fig015_SCPS253.gifFigure 11. Device power up without card inserted in system - Low to High PRES Topology
TCA5013 fig016_SCPS253.gifFigure 12. Device power up without card inserted in system - High to Low PRES Topology
TCA5013 fig017_SCPS253.gifFigure 13. Device Power Up With Card Inserted in System - Low to High PRES Topology
TCA5013 fig018_SCPS253.gifFigure 14. Device Power up with Card Inserted In System - High to Low PRES Topology