JAJSFN6G September 2009 – June 2018 TCA8418
PRODUCTION DATA.
BIT | NAME | DESCRIPTION |
---|---|---|
7 | AI |
Auto-increment for read and write operations; See below table for more information 0 = disabled 1 = enabled |
6 | GPI_E_CFG |
GPI event mode configuration 0 = GPI events are tracked when keypad is locked 1 = GPI events are not tracked when keypad is locked |
5 | OVR_FLOW_M |
Overflow mode 0 = disabled; Overflow data is lost 1 = enabled; Overflow data shifts with last event pushing first event out |
4 | INT_CFG |
Interrupt configuration 0 = processor interrupt remains asserted (or low) if host tries to clear interrupt while there is still a pending key press, key release or GPI interrupt 1 = processor interrupt is deasserted for 50 μs and reassert with pending interrupts |
3 | OVR_FLOW_IEN |
Overflow interrupt enable 0 = disabled; INT is not asserted if the FIFO overflows 1 = enabled; INT becomes asserted if the FIFO overflows |
2 | K_LCK_IEN |
Keypad lock interrupt enable 0 = disabled; INT is not asserted after a correct unlock key sequence 1 = enabled; INT becomes asserted after a correct unlock key sequence |
1 | GPI_IEN |
GPI interrupt enable to host processor 0 = disabled; INT is not asserted for a change on a GPI 1 = enabled; INT becomes asserted for a change on a GPI |
0 | KE_IEN |
Key events interrupt enable to host processor 0 = disabled; INT is not asserted when a key event occurs 1 = enabled; INT becomes asserted when a key event occurs |
Bit 7 in this register is used to determine the programming mode. If it is low, all data bytes are written to the register defined by the command byte. If bit 7 is high, the value of the command byte is automatically incremented after each byte is written, and the next data byte is stored in the corresponding register. Registers are written in the sequence shown in Table 9. Once the GPIO_PULL3 register (0x2E) is written to, the command byte returns to register 0. Registers 0 and 2F are reserved and a command byte that references these registers is not acknowledged by the TCA8418.
The keypad lock interrupt enable determines if the interrupt pin is asserted when the key lock interrupt (see Interrupt Status Register) bit is set.