JAJSHE4C may   2019  – june 2023 TCA9548A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Input
      2. 8.4.2 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Device Address
      3. 8.5.3 Bus Transactions
        1. 8.5.3.1 Writes
        2. 8.5.3.2 Reads
      4. 8.5.4 Control Register
      5. 8.5.5 RESET Input
      6. 8.5.6 Power-On Reset
  10.   Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11.   Power Supply Recommendations
    1. 9.1 Power-On Reset Requirements
  12. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  14.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1 Design Requirements

A typical application of the TCA9548A-Q1 contains one or more data pull-up voltages, VDPUX, one for the controller device (VDPUM) and one for each of the selectable target channels (VDPU0 – VDPU7). In the event where the controller device and all target devices operate at the same voltage, then VDPUM = VDPUX = VCC. In an application where voltage translation is necessary, additional design requirements must be considered to determine an appropriate VCC voltage.

The A0, A1, and A2 pins are hardware selectable to control the target address of the TCA9548A-Q1. These pins may be tied directly to GND or VCC in the application.

If multiple target channels are activated simultaneously in the application, then the total IOL from SCL/SDA to GND on the controller side is the sum of the currents through all pull-up resistors, Rp.

The pass-gate transistors of the TCA9548A-Q1 are constructed such that the VCC voltage can be used to limit the maximum voltage that is passed from one I2C bus to another.

Figure 9-2 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using data specified in the Electrical Characteristics table). In order for the TCA9548A-Q1 to act as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 9-2, Vpass(max) is 2.7 V when the TCA9548A-Q1 supply voltage is 4 V or lower, so the TCA9548A-Q1 supply voltage could be set to 3.3 V. Pull-up resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 9-1).