JAJSI83H May   2012  – September 2024 TCA9548A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Timing Requirements
    7. 5.7 Reset Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 RESET Input
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
      2. 7.5.2 Device Address
      3. 7.5.3 Bus Transactions
        1. 7.5.3.1 Writes
        2. 7.5.3.2 Reads
      4. 7.5.4 Control Register
      5. 7.5.5 RESET Input
      6. 7.5.6 Power-On Reset
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 商標
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
MIN MAX UNIT
STANDARD MODE
fscl I2C clock frequency 0 100 kHz
tsch I2C clock high time 4 μs
tscl I2C clock low time 4.7 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 250 ns
tsdh I2C serial-data hold time 0(1) μs
ticr I2C input rise time 1000 ns
ticf I2C input fall time 300 ns
tocf I2C output (SDn) fall time (10-pF to 400-pF bus) 300 ns
tbuf I2C bus free time between stop and start 4.7 μs
tsts I2C start or repeated start condition setup 4.7 μs
tsth I2C start or repeated start condition hold 4 μs
tsps I2C stop condition setup 4 μs
tvdL(Data) Valid-data time (high to low)(2) SCL low to SDA output low valid 1 μs
tvdH(Data) Valid-data time (low to high)(2) SCL low to SDA output high valid 0.6 μs
tvd(ack) Valid-data time of ACK condition ACK signal from SCL low
to SDA output low		 1 μs
Cb I2C bus capacitive load 400 pF
FAST MODE
fscl I2C clock frequency 0 400 kHz
tsch I2C clock high time 0.6 μs
tscl I2C clock low time 1.3 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 100 ns
tsdh I2C serial-data hold time 0(1) μs
ticr I2C input rise time 20 + 0.1Cb (3) 300 ns
ticf I2C input fall time 20 + 0.1Cb (3) 300 ns
tocf I2C output (SDn) fall time (10-pF to 400-pF bus) 20 + 0.1Cb (3) 300 ns
tbuf I2C bus free time between stop and start 1.3 μs
tsts I2C start or repeated start condition setup 0.6 μs
tsth I2C start or repeated start condition hold 0.6 μs
tsps I2C stop condition setup 0.6 μs
tvdL(Data) Valid-data time (high to low)(2) SCL low to SDA output low valid 1 μs
tvdH(Data) Valid-data time (low to high)(2) SCL low to SDA output high valid 0.6 μs
tvd(ack) Valid-data time of ACK condition ACK signal from SCL low
to SDA output low		 1 μs
Cb I2C bus capacitive load 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge the undefined region of the falling edge of SCL.
(2) Data taken using a 1-kΩ pull-up resistor and 50-pF load.
(3) Cb = total bus capacitance of one bus line in pF.