ZHCSPU9 数据表 | 德州仪器 TI.com.cn

JAJSNX3 February 2024 TCAN1465-Q1 , TCAN1469-Q1

ADVANCE INFORMATION

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

DMT|14
- MPSS087B
D|14
- MPDS177H

サーマルパッド・メカニカル・データ

発注情報

jajsnx3_oa

6.9 Switching Characteristics

parameters valid across -40℃ ≤ T_J ≤ 150℃ (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CAN TRANSCEIVER SWITCHING CHARACTERISTICS
t_{prop(TxD-busdom)}	Propagation delay time, high-to-low TXD edge to bus dominant (recessive to dominant)	45Ω ≤ R_L ≤ 65Ω, C_L = 100pF, R_CM = open; see Figure 9-4; V; The input signal on TXD shall have rising times (10% to 90%) and fall times (90% to 10%) of less than 10ns			80	ns
t_{prop(TxD-busrec)}	Propagation delay time, low-to-high TXD edge to bus recessive (dominant to recessive)				80	ns
t_sk(p)	Pulse skew (\|t_pHR – t_pLD\|)			10	40	ns
t_R/F	Differential output signal rise time		5	55	75	ns
t_{prop(busdom-RxD)}	Propagation delay time, bus dominant input to RxD low output	C_L(RXD) = 15pF; see Figure 9-5 ; The input signal on TXD shall have rising times (10% to 90%) and fall times (90% to 10%) of less than 10ns			110	ns
t_{prop(busrec-RxD)}	Propagation delay time, bus to recessive input to RXD high output				110	ns
t_PROP(LOOP1)	Total loop delay, driver input (TXD) to receiver output (RXD) dominant to recessive	45Ω ≤ R_L ≤ 65Ω, C_L = 100pF, C_L(RXD) = 15pF See Figure 9-6		100	190	ns
t_PROP(LOOP2)	Total loop delay, driver input (TXD) to receiver output (RXD) recessive to dominant	45Ω ≤ R_L ≤ 65Ω, C_L = 100pF, C_L(RXD) = 15pF See Figure 9-6		110	190	ns
CAN FD BIT TIMING
SIGNAL IMPROVEMENT CHARACTERISTICS
t_{PAS_REC_START}	Signal improvement start time of passive recessive phase	Measured from rising TXD edge with < 5ns slope at 50% threshold, to the end of the signal improvement phase; R_{DIFF_PAS_REC} ≥ MIN R_{DIFF_ACT_REC}; R_SE__CANH/L ≥ MIN R_{SE_SIC_REC} See Figure 9-6			530	ns
t_{ACT_REC_START}	Start time of active signal improvement phase	Measured from rising TXD edge with < 5ns slope at 50% threshold,			120	ns
t_{ACT_REC_END}	End time of active signal improvement phase	Measured from rising TXD edge with < 5ns slope at 50% threshold,	355			ns
t_ΔBit(Bus)	Transmitted bit width variation	Bus recessive bit length variation relative to TxD bit length, t_ΔBit(Bus) = t_Bit(Bus) - t_Bit(TXD) 45Ω ≤ R_L ≤ 65Ω; See Figure 9-6	–10		10	ns
t_ΔBIT(RxD)	Received bit width variation	RxD recessive bit length variation relative to TXD bit length, t_ΔBit(RxD) = t_Bit(RXD) - t_Bit(TXD) 45Ω ≤ R_L ≤ 65Ω; See Figure 9-6	–30		20	ns
t_Δ_REC	Receiver timing symmetry	RXD recessive bit length variation relative to bus bit length, t_ΔREC = t_Bit(RXD) - t_Bit(Bus) 45Ω ≤ R_L ≤ 65Ω; See Figure 9-6	–20		15	ns
SPI SWITCHING CHARACTERISTICS
f_SCK	SCK, SPI clock frequency	Normal, standby, listen and failsafe modes			4	MHz
f_SCK	SCK, SPI clock frequency	Sleep mode: If V_IO is present			10	kHz
t_SCK	SCK, SPI clock period	Normal, standby, listen and failsafe modes; see Figure 9-11	250			ns
t_SCK	SCK, SPI clock period	Sleep mode: If If V_IO is present; See Figure 9-11	100			µs
t_RSCK	SCK rise time	See Figure 9-10			40	ns
t_FSCK	SCK fall time	See Figure 9-10			40	ns
t_SCKH	SCK, SPI clock high	Normal, standby, listen and failsafe modes; see Figure 9-11	125			ns
t_SCKH	SCK, SPI clock high	Sleep mode: If V_IO is present; See Figure 9-11	500			ns
t_SCKL	SCK, SPI clock low	Normal, standby, listen and failsafe modes; see Figure 9-11	125			ns
t_SCKL	SCK, SPI clock low	Sleep mode: If V_IO is present	500			ns
t_CSS	Chip select setup time	See Figure 9-10	100			ns
t_CSH	Chip select hold time	See Figure 9-10	100			ns
t_CSD	Chip select disable time	See Figure 9-10	50			ns
t_SISU	Data in setup time	Normal, standby, listen and failsafe modes; see Figure 9-10	50			ns
t_SISU	Data in setup time	Sleep mode: If V_IO is present; see Figure 9-10	200			ns
t_SIH	Data in hold time	Normal, standby, listen and failsafe modes; see Figure 9-10	50			ns
t_SIH	Data in hold time	Sleep mode: If V_IO is present; see Figure 9-10	200			ns
t_SOV	Data out valid	Normal, standby, listen and failsafe modes; see Figure 9-11			80	ns
t_SOV	Data out valid	Sleep mode: If V_IO is present; see Figure 9-11			200	ns
t_RSO	Data out rise time	See Figure 9-11			40	ns
t_FSO	Data out fall time	See Figure 9-11			40	ns