JAJSO73A
December 2022 – June 2024
TCAN3403-Q1
,
TCAN3404-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
ESD Ratings, IEC Transients
6.4
Recommended Operating Conditions
6.5
Thermal Characteristics
6.6
Supply Characteristics
6.7
Dissipation Ratings
6.8
Electrical Characteristics
6.9
Switching Characteristics
6.10
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Pin Description
8.3.1.1
TXD
8.3.1.2
GND
8.3.1.3
VCC
8.3.1.4
RXD
8.3.1.5
VIO (TCAN3403-Q1 only)
8.3.1.6
CANH and CANL
8.3.1.7
STB (Standby)
8.3.1.8
SHDN (Shutdown)
8.3.2
CAN Bus States
8.3.3
TXD Dominant Timeout (DTO)
8.3.4
CAN Bus short-circuit current limiting
8.3.5
Thermal Shutdown (TSD)
8.3.6
Undervoltage Lockout
8.3.7
Unpowered Device
8.3.8
Floating pins
8.4
Device Functional Modes
8.4.1
Operating Modes
8.4.2
Normal Mode
8.4.3
Standby Mode
8.4.3.1
Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
8.4.4
Shutdown Mode
8.4.5
Driver and Receiver Function
9
Application Information Disclaimer
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
CAN Termination
9.2.2
Detailed Design Procedures
9.2.2.1
Bus Loading, Length and Number of Nodes
9.2.3
Application Curves
9.3
System Examples
9.3.1
ISO 11898-2 Compatibility of TCAN340x-Q1 Family of 3.3V CAN Transceivers
9.3.1.1
Introduction
9.3.1.2
Differential Signal
9.3.1.3
Common-Mode Signal
9.3.1.4
Interoperability of 3.3V CAN in 5V CAN Systems
9.4
Power Supply Recommendations
9.5
Layout
9.5.1
Layout Guidelines
9.5.2
Layout Example
10
Device and Documentation Support
10.1
ドキュメントの更新通知を受け取る方法
10.2
サポート・リソース
10.3
Trademarks
10.4
静電気放電に関する注意事項
10.5
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|8
MSOI002K
DRB|8
MPDS118K
DDF|8
MPDS569D
サーマルパッド・メカニカル・データ
DRB|8
QFND619
発注情報
JAJSO73A_pm
jajso73a_oa
9.2.1
Design Requirements