JAJSH69D January 2018 – June 2022 TCAN4550-Q1
PRODUCTION DATA
The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE.EINT0 and ILE.EINT1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RSVD | ARAL | PEDL | PEAL | WDIL | BOL | EWL | |
R | R/W | R/W | R/W | R/W | R/W | R/W | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EPL | ELOL | BEUL | BECL | DRXL | TOOL | MRAFL | TSWL |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TEFLL | TEFFL | TEFWL | TEFNL | TFEL | TCFL | TCL | HPML |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RF1LL | RF1FL | RF1WL | RF1NL | RF0LL | RF0FL | RF0WL | RF0NL |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:30 | RSVD | R | 0x0 | Reserved |
29 | ARAL | R/W | 0 | Access to Reserved Address Line |
28 | PEDL | R/W | 0 | Protocol Error in Data Phase Line |
27 | PEAL | R/W | 0 | Protocol Error in Arbitration Phase Line |
26 | WDIL | R/W | 0 | Watchdog Interrupt Line |
25 | BOL | R/W | 0 | Bus_Off Status Interrupt Line |
24 | EWL | R/W | 0 | Warning Status Interrupt Line |
23 | EPL | R/W | 0 | Error Passive Interrupt Line |
22 | ELOL | R/W | 0 | Error Logging Overflow Interrupt Line |
21 | BEUL | R/W | 0 | Bit Error Uncorrected Interrupt Line |
20 | BECL | R/W | 0 | Bit Error Corrected Interrupt Line |
19 | DRXL | R/W | 0 | Message stored to Dedicated Rx Buffer Interrupt Line |
18 | TOOL | R/W | 0 | Timeout Occurred Interrupt Line |
17 | MRAFL | R/W | 0 | Message RAM Access Failure Interrupt Line |
16 | TSWL | R/W | 0 | Timestamp Wraparound Interrupt Line |
15 | TEFLL | R/W | 0 | Tx Event FIFO Event Lost Interrupt Line |
14 | TEFFL | R/W | 0 | Tx Event FIFO Full Interrupt Line |
13 | TEFWL | R/W | 0 | Tx Event FIFO Watermark Reached Interrupt Line |
12 | TEFNL | R/W | 0 | Tx Event FIFO New Entry Interrupt Line |
11 | TFEL | R/W | 0 | Tx FIFO Empty Interrupt Line |
10 | TCFL | R/W | 0 | Transmission Cancellation Finished Interrupt Line |
9 | TCL | R/W | 0 | Transmission Completed Interrupt Line |
8 | HPML | R/W | 0 | High Priority Message Interrupt Line |
7 | RF1LL | R/W | 0 | Rx FIFO 1 Message Lost Interrupt Line |
6 | RF1FL | R/W | 0 | Rx FIFO 1 Full Interrupt Line |
5 | RF1WL | R/W | 0 | Rx FIFO 1 Watermark Reached Interrupt Line |
4 | RF1NL | R/W | 0 | Rx FIFO 1 New Message Interrupt Line |
3 | RF0LL | R/W | 0 | Rx FIFO 0 Message Lost Interrupt Line |
2 | RF0FL | R/W | 0 | Rx FIFO 0 Full Interrupt Line |
1 | RF0WL | R/W | 0 | Rx FIFO 0 Watermark Reached Interrupt Line |
0 | RF0NL | R/W | 0 | Rx FIFO 0 New Message Interrupt Line |