JAJSHT0 August 2019 TCAN4551-Q1
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WAKE_CONFIG | RSVD | CLK_REF | RSVD | RSVD | RSVD | ||
R/W | R | R/W | R | R | R | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPO2_CONFIG | TEST_MODE_EN | RSVD | nWKRQ_VOLTAGE | RSVD | RSVD | ||
R/W | R/W | R | R/W | R | R | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RSVD | FAIL_SAFE_EN | RSVD | GPO1_GPO_CONFIG | INH_DIS | nWKRQ_CONFIG | ||
R | R/W | R | R/W | R/W | R/W | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE_SEL | RSVD | RSVD | RSVD | DEVICE_RESET | SWE_DIS | TEST_MODE_CONFIG | |
R/W/U | R | R | R | R/W/U | R/W | R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:30 | WAKE_CONFIG | R/W | 2’b11 | WAKE_CONFIG: Wake pin configuration
00 = Disabled 01 = Rising edge 10 = Falling edge 11 = Bi-Directional – either edge |
29:28 | RSVD | R | 2'b00 | Reserved |
27 | CLK_REF | R/W | 1'b1 | CLK_REF: CLKIN/Crystal Frequency Reference
0 = 20 MHz 1 = 40 MHz |
26:24 | RSVD | R | 3'b000 | Reserved |
23:22 | GPO2_CONFIG | R/W | 2’b00 | GPO2_CONFIG: GPO2 Pin GPO Configuration
00 = No Action 01 = MCAN_INT 0 interrupt (Active low) 10 = Reserved 11 = Mirrors nINT pin (Active low) See NOTE section |
21 | TEST_MODE_EN | R/W | 1'b0 | TEST_MODE_EN: Test mode enable. When set device is in test mode
0 = Disabled 1 = Enabled |
20 | RSVD | R | 1'b0 | Reserved |
19 | nWKRQ_VOLTAGE | R/W | 1’b0 | nWKRQ_VOLTAGE: nWKRQ Pin GPO buffer voltage rail configuration: See (2)
0 = Internal voltage rail 1 = VIO voltage rail |
18:16 | RSVD | R | 3'b000 | Reserved |
15:14 | RSVD | R | 2’b00 | Reserved |
13 | FAIL_SAFE_EN | R/W | 1'b0 | FAIL_SAFE_EN: Fail safe mode enable:
0 = Disabled 1 = Enabled NOTE: Excludes power up fail safe. |
12 | RSVD | R | 1'b0 | Reserved |
11:10 | GPO1_GPO_CONFIG | R/W | 2’b01 | GPO1_GPO_CONFIG: GPO1 pin GPO1 function select
00 = SPI fault Interrupt (Active low) 01 = MCAN_INT 1 (Active low) 10 = Under voltage or thermal event interrupt (Active low) 11 = Reserved |
9 | INH_DIS | R/W | 1'b0 | INH_DIS: INH Pin Disable
0 = Pin enabled 1 = Pin disabled |
8 | nWKRQ_CONFIG | R/W | 1'b0 | nWKRQ_CONFIG: nWKRQ Pin Function
0 = Mirrors INH function 1 = Wake request interrupt |
7:6 | MODE_SEL | R/W | 2'b01 | MODE_SEL: Mode of operation select
00 = Sleep 01 = Standby 10 = Normal 11 = Reserved See NOTE section |
5 | RSVD | R | 1'b1 | When writing to this register, this bit must always be a 1 |
4 | RSVD | R | 1'b0 | Reserved |
3 | RSVD | R | 1'b0 | Reserved |
2 | DEVICE_RESET | R/WC | 1'b0 | DEVICE_RESET: Device Reset
0 = Current configuration 1 = Device resets to default NOTE: Same function as RST pin |
1 | SWE_DIS | R/W | 1'b0 | SWE_DIS: Sleep Wake Error Disable:
0 = Enabled 1 = Disabled NOTE: This disables the device from starting the four minute timer when coming out of sleep mode on a wake event. If this is enabled a SPI read or write must take place within this four minute window or the device will go back to sleep. This does not disable the function for initial power on or in case of a power on reset. |
0 | TEST_MODE_CONFIG | R/W | 1'b0 | Test Mode Configuration
0 = Phy Test with TXD/RXD_INT_PHY and EN_INT are mapped to external pins 1 = CAN Controller test with TXD/RXD_INT_CAN mapped to external pins |
NOTE