JAJSPJ8A december 2022 – august 2023 TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
PRODUCTION DATA
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Table 7-69, Figure 7-85, Table 7-70, and Figure 7-86 present timing requirements and switching characteristics for MMC1/2 – Default Speed Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
DS1 | tsu(cmdV-clkH) | Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge | 2.15 | ns | |
DS2 | th(clkH-cmdV) | Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge | 4.56 | ns | |
DS3 | tsu(dV-clkH) | Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge | 2.15 | ns | |
DS4 | th(clkH-dV) | Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge | 4.56 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC[x]_CLK | 25 | MHz | ||
DS5 | tc(clk) | Cycle time, MMC[x]_CLK | 40 | ns | |
DS6 | tw(clkH) | Pulse duration, MMC[x]_CLK high | 18.7 | ns | |
DS7 | tw(clkL) | Pulse duration, MMC[x]_CLK low | 18.7 | ns | |
DS8 | td(clkL-cmdV) | Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition | –3.53 | 3.53 | ns |
DS9 | td(clkL-dV) | Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition | –3.53 | 3.53 | ns |