JAJSLG2A April   2021  – September 2023 TDES960

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  CSI-2 Timing Specifications
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Receiver Port Control
        1. 7.4.5.1 Video Stream Forwarding
      6. 7.4.6  Input Jitter Tolerance
      7. 7.4.7  Adaptive Equalizer
        1. 7.4.7.1 Channel Requirements
        2. 7.4.7.2 Adaptive Equalizer Algorithm
        3. 7.4.7.3 AEQ Settings
          1. 7.4.7.3.1 AEQ Start-Up and Initialization
          2. 7.4.7.3.2 AEQ Range
          3. 7.4.7.3.3 AEQ Timing
          4. 7.4.7.3.4 AEQ Threshold
      8. 7.4.8  Channel Monitor Loop-Through Output Driver
        1. 7.4.8.1 Code Example for CMLOUT V3LINK RX Port 0:
      9. 7.4.9  RX Port Status
        1. 7.4.9.1 RX Parity Status
        2. 7.4.9.2 V3Link Decoder Status
        3. 7.4.9.3 RX Port Input Signal Detection
        4. 7.4.9.4 Line Counter
        5. 7.4.9.5 Line Length
      10. 7.4.10 Sensor Status
      11. 7.4.11 GPIO Support
        1. 7.4.11.1 GPIO Input Control and Status
        2. 7.4.11.2 GPIO Output Pin Control
        3. 7.4.11.3 Forward Channel GPIO
        4. 7.4.11.4 Back Channel GPIO
        5. 7.4.11.5 GPIO Pin Status
        6. 7.4.11.6 Other GPIO Pin Controls
      12. 7.4.12 RAW Mode LV / FV Controls
      13. 7.4.13 CSI-2 Protocol Layer
      14. 7.4.14 CSI-2 Short Packet
      15. 7.4.15 CSI-2 Long Packet
      16. 7.4.16 CSI-2 Data Identifier
      17. 7.4.17 Virtual Channel and Context
      18. 7.4.18 CSI-2 Mode Virtual Channel Mapping
        1. 7.4.18.1 Example 1
        2. 7.4.18.2 Example 2
      19. 7.4.19 CSI-2 Transmitter Frequency
      20. 7.4.20 CSI-2 Output Bandwidth
        1. 7.4.20.1 CSI-2 Output Bandwidth Calculation Example
      21. 7.4.21 CSI-2 Transmitter Status
      22. 7.4.22 Video Buffers
      23. 7.4.23 CSI-2 Line Count and Line Length
      24. 7.4.24 FrameSync Operation
        1. 7.4.24.1 External FrameSync Control
        2. 7.4.24.2 Internally Generated FrameSync
          1. 7.4.24.2.1 Code Example for Internally Generated FrameSync
      25. 7.4.25 CSI-2 Forwarding
        1. 7.4.25.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 7.4.25.2 Synchronized CSI-2 Forwarding
        3. 7.4.25.3 Basic Synchronized CSI-2 Forwarding
          1. 7.4.25.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 7.4.25.4 Line-Interleaved CSI-2 Forwarding
          1. 7.4.25.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 7.4.25.5 Line-Concatenated CSI-2 Forwarding
          1. 7.4.25.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 7.4.25.6 CSI-2 Replicate Mode
        7. 7.4.25.7 CSI-2 Transmitter Output Control
        8. 7.4.25.8 Enabling and Disabling CSI-2 Transmitters
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus
      2. 7.5.2  Second I2C Port
      3. 7.5.3  I2C Target Operation
      4. 7.5.4  Remote Target Operation
      5. 7.5.5  Remote Target Addressing
      6. 7.5.6  Broadcast Write to Remote Devices
        1. 7.5.6.1 Code Example for Broadcast Write
      7. 7.5.7  I2C Controller Proxy
      8. 7.5.8  I2C Controller Proxy Timing
        1. 7.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 7.5.9  Interrupt Support
        1. 7.5.9.1 Code Example to Enable Interrupts
        2. 7.5.9.2 V3Link Receive Port Interrupts
        3. 7.5.9.3 Interrupts on Forward Channel GPIO
        4. 7.5.9.4 Interrupts on Change in Sensor Status
        5. 7.5.9.5 Code Example to Readback Interrupts
        6. 7.5.9.6 CSI-2 Transmit Port Interrupts
      10. 7.5.10 Error Handling
        1. 7.5.10.1 Receive Frame Threshold
        2. 7.5.10.2 Port PASS Control
      11. 7.5.11 Timestamp – Video Skew Detection
      12. 7.5.12 Pattern Generation
        1. 7.5.12.1 Reference Color Bar Pattern
        2. 7.5.12.2 Fixed Color Patterns
        3. 7.5.12.3 Pattern Generator Programming
          1. 7.5.12.3.1 Determining Color Bar Size
        4. 7.5.12.4 Code Example for Pattern Generator
      13. 7.5.13 V3Link BIST Mode
        1. 7.5.13.1 BIST Operation
    6. 7.6 Register Maps
      1. 7.6.1 Main Registers
      2. 7.6.2 Indirect Access Registers
        1. 7.6.2.1 PATGEN_And_CSI-2 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 VDD Power Supply
      2. 8.4.2 Power-Up Sequencing
        1. 8.4.2.1 PDB Pin
        2. 8.4.2.2 System Initialization
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground
        2. 8.5.1.2 Routing V3Link Signal Traces and PoC Filter
        3. 8.5.1.3 CSI-2 Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 CSI-2 Timing Specifications

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETERTEST CONDITIONSPIN OR FREQUENCYMINTYPMAXUNIT
HSTX DRIVER
HSTXDBRData rateREFCLK = 23 MHzCSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N3687361472Mbps
REFCLK = 25 MHz4008001600Mbps
REFCLK = 26 MHz4168321664Mbps
fCLKDDR clock frequencyREFCLK = 23 MHzCSI0_CLKP, CSI0_CLKN, CSI1_CLKP, CSI1_CLKN184368736MHz
REFCLK = 25 MHz200400800MHz
REFCLK = 26 MHz208416832MHz
ΔVCMTX(HF)Common mode voltage variations HFAbove 450 MHzCSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN15mVRMS
ΔVCMTX(LF)Common mode voltage variations LFBetween 50 and 450 MHz25mVRMS
tRHS
tFHS		20% to 80% rise and fall HSHS data rates ≤ 1 Gbps (UI ≥ 1 ns)0.3UI
HS data rates > 1 Gbps (UI ≤ 1 ns) but less than 1.5 Gbps (UI ≥ 0.667 ns)0.35UI
Applicable when supporting maximum HS data rates ≤ 1.5 Gbps.100ps
Applicable for all HS data rates when supporting > 1.5 Gbps.0.4UI
Applicable for all HS data rates when supporting > 1.5 Gbps.50ps
SDDTXTX differential return lossfLPMAXHS data rates <1.5 Gbps-18dB
fH-9dB
fMAX-3dB
fLPMAXHS data rates >1.5 Gbps-18dB
fH-4.5dB
fMAX-2.5dB
SCCTXTX common mode return lossDC to fLPMAXAll HS data rates-20dB
fH-15dB
fMAX-9dB
LPTX DRIVER
tRLPRise time LP(1)15% to 85% rise timeCSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN25ns
tFLPFall time LP(1)15% to 85% fall time25ns
tREOTRise time post-EoT(1)30%-85% rise time35ns
tLP-PULSE-TXPulse width of the LP exclusive-OR clock(1)First LP exclusive-OR clock pulse after Stop state or last pulse before Stop state40ns
All other pulses20ns
tLP-PER-TXPeriod of the LP exclusive-OR clock90ns
DV/DtSRSlew rate(1)CLOAD = 0 pF500mV/ns
CLOAD = 5 pF300mV/ns
CLOAD = 20 pF250mV/ns
CLOAD = 70 pF150mV/ns
CLOAD = 0 to 70 pF (falling edge only), data rate ≤ 1.5 Gbps30mV/ns
CLOAD = 0 to 70 pF (falling edge only), data rate ≤ 1.5 Gbps30mV/ns
CLOAD = 0 to 70 pF (falling edge only), data rate > 1.5 Gbps25mV/ns
CLOAD = 0 to 70 pF (falling edge only), data rate > 1.5 Gbps25mV/ns
CLOAD = 0 to 70 pF (falling edge only)(2)(3)30 - 0.075×(VO,INST - 700)mV/ns
CLOAD = 0 to 70 pF (falling edge only)(4)(5)25 - 0.0625×(VO,INST - 550)mV/ns
CLOADLoad capacitance(1)070pF
DATA-CLOCK TIMING (Figure 6-6, Figure 6-7)
UIINSTUI instantaneousIn 1, 2, 3, or 4 lane configuration
Data rate = 368 Mbps to 1.664 Gbps		CSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN0.62.7ns
ΔUIUI variationUI ≥ 1 ns (Figure 6-5)-10%10%UI
UI < 1 ns (Figure 6-5)-5%5%UI
tSKEW(TX)Data to clock skew (measured at transmitter)
Skew between clock and data from ideal center		Data rate ≤ 1 Gbps (Figure 6-5)-0.150.15UIINST
1 Gbps ≤ Data rate ≤ 1.5 Gbps (Figure 6-5)-0.20.2UIINST
tSKEW(TX) staticStatic data to clock skewData rate > 1.5 Gbps-0.20.2UIINST
tSKEW(TX) dynamicDynamic data to clock skew-0.150.15UIINST
ISIChannel ISI0.2UIINST
GLOBAL TIMING (Figure 6-6, Figure 6-7)
tCLK-POSTHS exit CSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN60 + 52×UIINSTns
tCLK-PRETime HS clock shall be driver prior to any associated Data Lane beginning the transition from LP to HS mode8UIINST
tCLK-PREPAREClock Lane HS Entry3895ns
tCLK-SETTLETime interval during which the HS receiver shall ignore any Clock Lane HS transitions95300ns
tCLK-TERM-ENTime-out at Clock Lane Display Module to enable HS TerminationTime for Dn to reach VTERM-EN38ns
tCLK-TRAILTime that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst60ns
tCLK-PREPARE + tCLK-ZEROTCLK-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock300ns
tD-TERM-ENTime for the Data Lane receiver to enable the HS line terminationCSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKNTime for Dn to reach V-TERM-EN35 + 4×UIINSTns
tEOTTransmitted time interval from the start of tHS-TRAIL to the start of the LP-11 state following a HS burst105 + 12×UIINSTns
tHS-EXITTime that the transmitter drives LP=11 following a HS burst100ns
tHS-PREPAREData Lane HS Entry40 + 4×UIINST85 + 6×UIINSTns
tHS-PREPARE + tHS-ZEROtHS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence145 + 10×UIINSTns
tHS-SETTLETime interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of tHS-SETTLE85 + 6×UIINST145 + 10×UIINSTns
tHS-SKIPTime interval during which the HS-RX ignores any transitions on the Data Lane, following a HS burst. The end point of the interval is defined as the beginning of the LP-11 state following the HS burst.4055 + 4×UIINSTns
tHS-TRAILData Lane HS ExitCSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN60 + 4×UIINSTns
tLPXTransmitted length of LP state50ns
tWAKEUPRecovery Time from Ultra Low Power State (ULPS)1ms
tINITInitialization periodCSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN100µs
(1) CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be <10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay.
(2) When the output voltage is between 700 mV and 930 mV
(3) Applicable when the supported data rate ≤ 1.5 Gbps
(4) When the output voltage is between 550 mV and 790 mV
(5) Applicable when the supported data rate > 1.5 Gbps.