JAJSOW0A July 2022 – July 2023 TDP1204
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
VCC | 1 | P | 3.3-V power supply |
HPDOUT_SEL | 2 | I 2-level (PD) |
HPDOUT_SEL. Selects whether HPD_OUT pin is push, pull, or open-drain. Open-drain is not supported in pin-strap mode. Therefore this pin should be left floating or pull-down to GND. |
TEST1 | 3 | O | Test1. For TI internal use only. This pin can be left
unconnected. |
CTLEMAP_SEL | 4 | I 4-level (PU/PD) |
CTLE Map select. When TDP1204 is configured in pin-strap mode, this pin selects the CTLE Map used. Table 8-8 lists more details. Also in pin-strap this pin will control whether or not AEQ is enabled. Table 8-9 lists more details. In I2C mode, CTLE map and AEQ enable is determined by registers. |
LINEAR_EN | 5 | I 4-level (PU/PD) |
In pin-strap mode, selects whether TDP1204 operates in linear or limited redriver mode. Table 8-5 lists more details. |
VCC | 6 | P | 3.3-V power supply |
EN | 7 | I 2-level (PU) |
When low, TDP1204 will be held in reset. The IN_D[2:0], IN_CLK, OUT_D[2:0] and OUT_CLK pins will be held in high impedance while EN is low. On rising edge of EN, the device will sample four-level inputs and function based on the sampled state of the pins. This pin has an internal 250-k pull-up to VIO. |
EQ1 | 8 | I 4-level (PU/PD) |
EQ1 pin setting when TDP1204 is configured for pin strap mode; works in conjunction with EQ0; Table 8-6 lists the settings. In I2C mode, EQ settings are controlled through the registers. |
IN_D2p | 9 | I | Channel 2 differential positive input |
IN_D2n | 10 | I | Channel 2 differential negative input |
HPD_OUT | 11 | O | Hot plug detect output to source side. If not used, then this pin can be left floating. If used, then it is recommended to have an external 220k resistor to GND on this pin. |
IN_D1p | 12 | I | Channel 1 differential positive input. |
IN_D1n | 13 | I | Channel 1 differential negative input. |
VIO | 14 | P | Voltage supply for I/Os. Table 8-2 lists more details. |
IN_D0p | 15 | I | Channel 0 differential positive input |
IN_D0n | 16 | I | Channel 0 differential negative input |
MODE | 17 | I 4-level (PU/PD) |
Mode control pin. Selects between pin-strap and I2C mode. For more details, refer to Section 8.3.1. |
IN_CLKp | 18 | I | Clock differential positive input |
IN_CLKn | 19 | I | Clock differential negative input |
VCC | 20 | P | 3.3-V power supply |
SCL/CFG0 | 21 | I | I2C Clock/CFG0: when TDP1204 is configured for I2C mode, this pin will function as the I2C clock. Table 8-18 lists how this pin otherwise functions as CFG0. |
SDA/CFG1 | 22 | I/O | I2C Data / CFG1: when TDP1204 is configured for I2C mode, this pin will function as the I2C clock. Table 8-19 lists how this pin will otherwise function as CFG1. |
AC_EN | 23 | I 2-level (PD) |
In pin-strap mode, the AC_EN pin selects whether high speed
transmitters are externally AC or DC-coupled. 0: DC-coupled 1: AC-coupled |
LV_DDC_SCL | 24 | I/O | Low voltage side bidirectional DDC clock line. Internally pulled-up to VIO. |
LV_DDC_SDA | 25 | I/O | Low voltage side bidirectional DDC data line. Internally pulled-up to VIO. |
HV_DDC_SDA | 26 | I/O | High voltage
side bidirectional DDC data line. Pull-up externally to HDMI 5-V. |
HV_DDC_SCL | 27 | I/O | High voltage side bidirectional DDC clock line. Pull-up externally to HDMI 5-V. |
VCC | 28 | P | 3.3-V power supply |
TXPRE | 29 | I 4-level (PU/PD) |
TX pre-emphasis control: in pin-strap mode with limited enabled, this pin controls TX EQ. In pin-strap with linear and AEQ enabled, this pin will adjust the adapted value. Table 8-15 lists the available settings for the TXPRE when operating in pin strap mode. In I2C mode, Tx pre-emphasis is controlled through the registers. |
OUT_CLKn | 30 | O | TMDS data clock differential negative output |
OUT_CLKp | 31 | O | TMDS data clock differential positive output |
HPD_IN | 32 | I 2-level (PD) |
Hot plug detect input from sink side. This pin has an internal pull-down resistor and is fail-safe. |
OUT_D0n | 33 | O | TMDS data 0 differential negative output |
OUT_D0p | 34 | O | TMDS data 0 differential positive output |
ADDR/EQ0 | 35 | I 4-level (PU/PD) |
Address bit for
I2C programming when TDP1204 is configured for I2C mode.
Table 8-22 lists more details. EQ0 pin setting when TDP1204 is configured for pin strap mode; works in conjunction with EQ1; Table 8-6 lists the EQ pin settings. In I2C mode, EQ settings are controlled through the registers. |
OUT_D1n | 36 | O | TMDS data 1 differential negative output |
OUT_D1p | 37 | O | TMDS data 1 differential positive output |
TXSWG | 38 | I 4-level (PU/PD) |
TX output swing control: 4 settings. This pin is only used in pin strap mode. Table 8-17 lists the available TX swing settings. In I2C mode, Tx output swing is controlled through the registers. |
OUT_D2n | 39 | O | TMDS data 2 differential negative output |
OUT_D2p | 40 | O | TMDS data 2 differential positive output |
Thermal Pad | — | Thermal pad. Connect to a solid ground plane. |