JAJSOW0A July   2022  – July 2023 TDP1204

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  4-Level Inputs
      2. 8.2.2  I/O Voltage Level Selection
      3. 8.2.3  HPD_OUT
      4. 8.2.4  Lane Control
      5. 8.2.5  Swap
      6. 8.2.6  Linear and Limited Redriver
      7. 8.2.7  Main Link Inputs
      8. 8.2.8  Receiver Equalizer
      9. 8.2.9  CTLE Bypass
      10. 8.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 8.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 8.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 8.2.12 Input Signal Detect
      13. 8.2.13 Main Link Outputs
        1. 8.2.13.1 Transmitter Bias
        2. 8.2.13.2 Transmitter Impedance Control
        3. 8.2.13.3 TX Slew Rate Control
        4. 8.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 8.2.13.5 TX Swing Control
      14. 8.2.14 DDC Buffer
      15. 8.2.15 HDMI DDC Capacitance
      16. 8.2.16 DisplayPort
    3. 8.3 Device Functional Modes
      1. 8.3.1 MODE Control
        1. 8.3.1.1 I2C Mode (MODE = "F")
        2. 8.3.1.2 Pin Strap Modes
          1. 8.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 8.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ and DDC Buffer Enabled
          3. 8.3.1.2.3 Pin-Strap HDMI 2.1 Function (MODE = "1"): Flexible RX EQ and DDC Buffer Enabled
          4. 8.3.1.2.4 Pin-Strap HDMI 2.1 Function (MODE = "R"): Flexible Rx EQ and DDC Buffer Disabled
      2. 8.3.2 DDC Snoop Feature
        1. 8.3.2.1 HDMI Type
        2. 8.3.2.2 HDMI 2.1 FRL Snoop
      3. 8.3.3 Low Power States
    4. 8.4 Programming
      1. 8.4.1 Pseudocode Examples
        1. 8.4.1.1 HDMI 2.1 Source Example with DDC Snoop and DDC Buffer Enabled
        2. 8.4.1.2 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
      2. 8.4.2 TDP1204 I2C Address Options
      3. 8.4.3 I2C Target Behavior
    5. 8.5 Register Maps
      1. 8.5.1 TDP1204 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Source-Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pre-Channel (LAB)
        2. 9.2.2.2 Post-Channel (LCD)
        3. 9.2.2.3 Common Mode Choke
        4. 9.2.2.4 ESD Protection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Sink-Side Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedures
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Supply Decoupling
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントのサポート
      1. 10.1.1 関連資料
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Switching Characteristics

over recommended voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Redriver
fHDMI14_open Maximum HDMI 1.4 clock frequency at which TX termination is assured to be open HDMI1.4; 25 MHz ≤ IN_CLK ≤ 340 MHz; TXTERM_AUTO_HDMI14 = 0h; TERM = 2h; TX is DC-coupled; 165 MHz
fHDMI14_300 Minimum HDMI 1.4 clock frequency at which TX termination is assured to be 300-ohms HDMI1.4; 25 MHz ≤ IN_CLK ≤ 340 MHz; TXTERM_AUTO_HDMI14 = 0h; TERM = 2h; TX is DC-coupled; 250 MHz
tAEQ_DONE Time from start of FRL link training to AEQ complete for 3 Gbps. 0.7 ms
tAEQ_DONE Time from start of FRL link training to AEQ complete for 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps 0.5 ms
tPD Propagation delay time At TTP4; 90 220 ps
tSK1(T) Data lane Intra-pair output skew with worse case skew at inputs At TTP4; With 0.15 UI skew at input; At 12 Gbps; LTP5, 6, 7, or 8; TXFFE0; TX termination 100-Ω; Linear mode; 0.15 UI
tSK1(T) Clock lane Intra-pair output skew with zero intra-pair skew at inputs At TTP4; No intra-pair skew at input; 6 Gbps with 150 MHz clock; TX termination 100-Ω; Limited mode; 0.10 0.15 UI
tSK1(T) Data lane Intra-pair output skew with zero intra-pair skew at inputs At TTP4; No intra-pair skew at input; At 12 Gbps; LTP5, 6, 7, or 8; TXFFE0; TX termination 100-Ω; Limited mode; 0.053 0.11 UI
tSK2(T) Inter-pair output skew At TTP4; At 12 Gbps; LTP5, 6, 7, or 8; TXFFE0; 30 ps
tRF-CLK-14 Transition time (rise and fall time) for clock lane when operating at HDMI1.4  At TTP4; 20% to 80%; Clock Frequency = 300 MHz; 75 600 ps
tRF-CLK-20 Transition time (rise and fall time) for clock lane when operating at HDMI 2.0   At TTP4; 20% to 80%; Clock Frequency = 150 MHz; 75 600 ps
tRF_14 Transition time (rise and fall time) for data lanes when operating at HDMI 1.4  At TTP4; 20% to 80%; DR = 3 Gbps; SLEW_HDMI14 = default; PRBS7 pattern; Clock Frequency = 300 MHz; 75 195 ps
tRFDAT_20 Transition time (rise and fall time) for data lanes when operating at HDMI 2.0   At TTP4; 20% to 80%; DR = 6 Gbps; SLEW_HDMI20 = default; PRBS7 pattern; Clock Frequency = 150 MHz; 42.5 115 ps
tSLEW_FRL Single-ended TX slew rate for data lanes when operating at HDMI 2.1 FRL At TTP4; Slope at 50% level; All FRL DR up to 12 Gbps; SLEW_HDMI21 = Default; clock pattern of 128 zeros and 128 ones; 16 mV/ps
tTRANS_3G Transition bit duration when de-emphasis/pre-emphasis is enabled At TTP4; DR = 3 Gbps; Clock pattern of 128 zeros followed by 128 ones; 0.4 1 UI
tTRANS_6G Transition bit duration when de-emphasis/pre-emphasis is enabled At TTP4; DR = 6 Gbps; Clock pattern of 128 zeros followed by 128 ones; 0.4 1 UI
tTRANS_8G Transition bit duration when de-emphasis/pre-emphasis is enabled At TTP4; DR = 8 Gbps; Clock pattern of 128 zeros followed by 128 ones; 0.4 1 UI
tTRANS_10G Transition bit duration when de-emphasis/pre-emphasis is enabled At TTP4; DR = 10 Gbps; Clock pattern of 128 zeros followed by 128 ones; 0.5 1.1 UI
tTRANS_12G Transition bit duration when de-emphasis/pre-emphasis is enabled At TTP4; DR = 12 Gbps; Clock pattern of 128 zeros followed by 128 ones; 0.6 1.3 UI
HPD
tHPD_PD HPD_IN to HPD_OUT propagation delay Refer to Figure 7-7 100 µs
tHPD_PWRDOWN HPD_IN debounce time before declaring Powerdown.  Enter Powerdown if HPD_IN is low after debounce time. Refer to Figure 7-7 2 4 ms
tHPD_STANDBY HPD_IN debounce time required for exiting Powerdown to Standby. Exit Powerdown if HPD_IN is high after debounce time. Refer to Figure 7-8 2 4 ms
Standby
tSTANDBY_ENTRY Detection of electrical idle to entry into Standby. HPD_IN = H; 300 µs
tSIGDET_DB Maximum differential signal glitch time rejected during debounce before transitioning from standby to active HPD_IN = H; 25 µs
tSIGDET_DB Maximum differential signal glitch time rejected during debounce before transitioning from active to standby HPD_IN = H; 50 ns
tSTANDBY_EXIT Detection of differential signal to exit from Standby to Active state HPD_IN = H; Does not include AEQ time if AEQ_TX_DELAY_EN = 1; 200 µs
DDC Buffer
fSCL DDC buffer frequency 100 kHz
tPLH1 Propagation delay time. Low-to-high-level output. VIO set to 1.2 V LVCMOS levels.  LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 1400 ns
Propagation delay time. Low-to-high-level output. VIO set to 1.8 V LVCMOS levels.  LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 1400 ns
Propagation delay time. Low-to-high-level output. VIO set to 3.3 V LVCMOS levels.  LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 1400 ns
tPLH2 Propagation delay time. Low-to-high-level output. VIO set to 1.2 V LVCMOS levels. HV to LV;  CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 410 ns
Propagation delay time. Low-to-high-level output. VIO set to 1.8 V LVCMOS levels. HV to LV;  CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 410 ns
Propagation delay time. Low-to-high-level output. VIO set to 3.3 V LVCMOS levels. HV to LV;  CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 410 ns
tPHL1 Propagation delay time. High to low-level output. VIO set to 1.2 V LVCMOS. LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 1200 ns
Propagation delay time. High to low-level output. VIO set to 1.8 V LVCMOS. LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 1200 ns
Propagation delay time. High to low-level output. VIO set to 3.3 V LVCMOS. LV to HV; CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 1200 ns
tPHL2 Propagation delay time. High to low-level output. VIO set to 1.2 V LVCMOS. HV to LV;  CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 535 ns
Propagation delay time. High to low-level output. VIO set to 1.8 V LVCMOS. HV to LV;  CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 535 ns
Propagation delay time. High to low-level output. VIO set to 3.3 V LVCMOS. HV to LV;  CLV_BUS = CHV_BUS = 50 pF; DDC_LV_DCC_EN = 1'b1; 535 ns
tLV_FALL LV side fall time for 1.2-V LVCMOS 70% to 30%;  CLV_BUS = CHV_BUS = 50 pF; 75 260 ns
LV side fall time for 1.8-V LVCMOS 70% to 30%;  CLV_BUS = CHV_BUS = 50 pF; 75 260 ns
LV side fall time for 3.3-V LVCMOS 70% to 30%;  CLV_BUS = CHV_BUS = 50 pF; 75 260 ns
tHV_FALL HV side fall time 70% to 30%;  CLV_BUS = CHV_BUS = 50 pF; 75 260 ns
tLV_RISE LV side rise time for 1.2-V LVCMOS 30% to 70%;  CLV_BUS = CHV_BUS = 50 pF; Pulled up to VIO using RPULV; 300 670 ns
LV side rise time for 1.8-V LVCMOS 30% to 70%;  CLV_BUS = CHV_BUS = 50 pF; Pulled up to VIO using RPULV; 300 670 ns
LV side rise time for 3.3-V LVCMOS 30% to 70%;  CLV_BUS = CHV_BUS = 50 pF; Pulled up to VIO using RPULV; 300 670 ns
tHV_RISE_50pF HV side rise time (50 pF load)  30% to 70%;  CLV_BUS = CHV_BUS = 50 pF; VCC = 3.0 V; HDMI5V = 5.3 V; Pulled up to HDMI5V using RPUHV; 225 ns
tHV_RISE_750pF HV side rise time (750 pF load) 30% to 70%;  CLV_BUS = 50 pF; CHV_BUS = 750 pF; VCC = 3.0 V; HDMI5V = 5.3 V; Pulled up to HDMI5V using RPUHV; 1250 ns