JAJSVM2 November   2024 TDP142-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Supply Characteristics
    6. 5.6 Control I/O DC Electrical Characteristics
    7. 5.7 DP Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DisplayPort
      2. 6.3.2 Configuration Jumper Levels
      3. 6.3.3 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 Linear EQ Configuration
      4. 6.4.4 Operation Timing – Power Up
    5. 6.5 Programming
  9. 7 Register Maps
    1. 7.1 TDP142-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ESD Protection
    2. 8.2 Typical Application
      1. 8.2.1 Source Application Implementation
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detail Design Procedure
      2. 8.2.2 Sink Application Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4.3 Linear EQ Configuration

The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 6-2 details the gain value for each available combination when TDP142-Q1 is in GPIO mode. The I2C mode can do the same option or even individual lane EQ setting by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, and DP3EQ_SEL.

Table 6-2 TDP142-Q1 Receiver Equalization Control
REGISTER(S): DP0EQ_SEL, DP1EQ_SEL,
DP2EQ_SEL, OR DP3EQ_SEL
EQUALIZATION SETTING #		 DPEQ1 PIN LEVEL DPEQ0 PIN LEVEL EQ GAIN AT 2.7/4.05/5GHz MINUS GAIN AT 100MHz
(dB)
0 0 0 0.4/0.8/0.83
1 0 R 2.0/3.1/3.4
2 0 F 3.0/4.6/5.0
3 0 1 4.2/6.0/6.5
4 R 0 5.0/7.0/7.5
5 R R 6.0/8.0/8.4
6 R F 6.5/8.7/9.1
7 R 1 7.2/9.4/9.8
8 F 0 7.8/10.0/10.3
9 F R 8.3/10.4/10.7
10 F F 8.7/10.7/10.9
11 F 1 9.1/11.1/11.2
12 1 0 9.4/11.3/11.3
13 1 R 9.7/11.5/11.5
14 1 F 10.0/11.7/11.6
15 1 1 10.2/11.8/11.7