JAJSVM2 November   2024 TDP142-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Supply Characteristics
    6. 5.6 Control I/O DC Electrical Characteristics
    7. 5.7 DP Electrical Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 DisplayPort
      2. 6.3.2 Configuration Jumper Levels
      3. 6.3.3 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration in I2C Mode
      3. 6.4.3 Linear EQ Configuration
      4. 6.4.4 Operation Timing – Power Up
    5. 6.5 Programming
  9. 7 Register Maps
    1. 7.1 TDP142-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ESD Protection
    2. 8.2 Typical Application
      1. 8.2.1 Source Application Implementation
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detail Design Procedure
      2. 8.2.2 Sink Application Implementation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Control I/O DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4-level Inputs
IIH High level input current VCC = 3.6V; VIN = 3.6V 20 60 µA
IIL Low level input current VCC = 3.6V; VIN = 0V –100 -40 µA
4-Level VTH Threshold 0 / R VCC = 3.3V 0.55 V
4-Level VTH Threshold R/ Float VCC = 3.3V 1.65 V
4-Level VTH Threshold Float / 1 VCC = 3.3V 2.7 V
RPU Internal pullup resistance 48 kΩ
RPD Internal pulldown resistance 98 kΩ
2-State CMOS Input
VIH High-level input voltage VCC = 3.0V 2 3.6 V
VIL Low-level input voltage VCC = 3.6V 0 0.8 V
RPD Internal pulldown resistance for HPDIN, CADSNK 400 500 600 kΩ
RPD Internal pulldown resistance for DPEN 400 500 600 kΩ
IIH_DPEN High-level input current for DPEN VIN = 3.6V –11 11 µA
IIL_DPEN Low-level input current for DPEN VIN = GND, VCC = 3.6V –1 1 µA
IIH_HPD_CAD High-level input current for HPDIN, CADSNK VIN = 3.6V –11 11 µA
IIL_HPD_CAD Low-level input current for HPDIN, CADSNK VIN = GND, VCC = 3.6V –1 1 µA
I2C Control Pins (SCL, SDA)
VIH_3p3V High-level input voltage when configured for 3.3V I2C level I2C_EN = 1 2.0 3.6 V
VIL_3p3V Low-level input voltage when configured for 3.3V I2C level I2C_EN = 1 0 0.8 V
VIH_1p8V High-level input voltage when configured for 1.8V I2C level I2C_EN = F 1.2 V
VIL_1p8V Low-level input voltage when configured for 1.8V I2C level I2C_EN = F 0 0.6 V
VOL Low-level output voltage I2C_EN = 0; IOL = 6mA 0 0.4 V
IOL Low-level output current I2C_EN = 0; VOL = 0.4V 20 mA
II(I2C) Input current 0.1 × V(I2C) < Input voltage < 3.3V –1 1 µA
CI(I2C) Input capacitance 10 pF
C(I2C_FM+_BUS) I2C bus capacitance for FM+ (1MHz) 150 pF
C(I2C_FM_BUS) I2C bus capacitance for FM (400kHz) 150 pF
R(EXT_I2C_FM+) External resistors on both SDA and SCL when operating at FM+ (1MHz) C(I2C_FM+_BUS) = 150pF 620 820 910 Ω
R(EXT_I2C_FM) External resistors on both SDA and SCL when operating at FM (400kHz) C(I2C_FM_BUS) = 150pF 620 1500 2200 Ω