JAJSDS8C September   2017  – May 2019 TDP142

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      ディスプレイ
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DisplayPort
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 6. General Registers
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
        1. Table 7. DisplayPort Control/Status Registers (0x10)
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
        1. Table 8. DisplayPort Control/Status Registers (0x11)
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
        1. Table 9. DisplayPort Control/Status Registers (0x12)
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
        1. Table 10. DisplayPort Control/Status Registers (0x13)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Source Application Implementation
        1. 9.2.1.1 Design Requirement
        2. 9.2.1.2 Detail Design Procedure
      2. 9.2.2 Sink Application Implementation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連リンク
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 AC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DisplayPort Transmitter (OUTDP[3:0]p or OUTDP[3:0]n)
VTX(DIFF-PP) Transmitter dynamic differential voltage swing range. 1500 mVPP
VTX(RCV-DETECT) Amount of voltage change allowed during receiver detection 600 mV
VTX(CM-AC-PP-ACTIVE) Tx AC common-mode voltage active Max mismatch from Txp + Txn for both time and amplitude 100 mVPP
VTX(IDLE-DIFF-AC-PP) AC electrical idle differential peak-to-peak output voltage At package pins 0 10 mV
VTX(IDLE-DIFF-DC) DC electrical idle differential output voltage At package pins after low pass filter to remove AC component 0 14 mV
RTX(DIFF) Differential impedance of the driver 75 120 Ω
CAC(COUPLING) AC coupling capacitor 75 265 nF
RTX(CM) Common-mode impedance of the driver Measured with respect to AC ground over
0–500 mV		 18 30 Ω
CTX(PARASITIC) TX input capacitance for return loss At package pins, at 2.5GHz 1.25 pF
RLTX(DIFF) Differential return loss 50 MHz – 1.25 GHz at 90 Ω -15 dB
2.5 GHz at 90 Ω -12 dB
RLTX(CM) Common-mode return loss 50 MHz – 2.5 GHz at 90 Ω -13 dB
ITX(SHORT) TX short circuit current TX± shorted to GND 67 mA
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC) 0 0 V
AC Characteristics
Crosstalk Differential crosstalk between TX and RX signal pairs at 2.5 GHz –30 dB
C(P1dB-LF) Low frequency 1-dB compression point at 100 MHz, 200 mVPP < VID
< 2000 mVPP 		1300 mVPP
C(P1dB-HF) High frequency 1-dB compression point at 2.5 GHz, 200 mVPP < VID
< 2000 mVPP 		1300 mVPP
fLF Low frequency cutoff 200 mVPP< VID < 2000 mVPP 20 50 kHz
TX output deterministic jitter 200 mVPP < VID < 2000 mVPP, PRBS7, 5 Gbps 0.05 UIpp
200 mVPP < VID < 2000 mVPP, PRBS7, 8.1 Gbps 0.08 UIpp
TX output total jitter 200 mVPP < VID < 2000 mVPP, PRBS7, 5 Gbps 0.08 UIpp
200 mVPP < VID < 2000 mVPP, PRBS7, 8.1 Gbps 0.135 UIpp
DisplayPort Receiver (INDP[3:0]p or INDP[3:0]n)
VID(PP) Peak-to-peak input differential dynamic voltage range 2000 V
VIC Input common mode voltage 0 2 V
C(AC) AC coupling capacitance 75 200 nF
EQ(DP) Receiver equalization DPEQ[1:0] at 4.05 GHz 14 dB
dR Data rate HBR3 8.1 Gbps
R(ti) Input termination resistance 80 100 120 Ω
AUXp or AUXn
V(AUXP_DC_CM) AUX Channel DC common mode voltage for AUXp VCC = 3.3 V 0 0.4 V
V(AUXN_DC_CM) AUX Channel DC common mode voltage for AUXn VCC = 3.3 V 2.7 3.6 V