JAJSOC1H March   2000  – March 2022 TFP401 , TFP401A

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Digital I/O Electrical Characteristics
    6. 7.6 DC Electrical Characteristics
    7. 7.7 AC Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TMDS Pixel Data and Control Signal Encoding
      2. 9.3.2 TFP401/401A Clocking and Data Synchronization
      3. 9.3.3 TFP401/401A TMDS Input Levels and Input Impedance Matching
      4. 9.3.4 TFP401A Incorporates HSYNC Jitter Immunity
    4. 9.4 Device Functional Modes
      1. 9.4.1 TFP401/401A Modes of Operation
      2. 9.4.2 TFP401/401A Output Driver Configurations
        1. 9.4.2.1 Output Driver Power Down
        2. 9.4.2.2 Drive Strength
        3. 9.4.2.3 Time-Staggered Pixel Output
        4. 9.4.2.4 Power Management
        5. 9.4.2.5 Sync Detect
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data and Control Signals
        2. 10.2.2.2 Configuration Options
        3. 10.2.2.3 Power Supplies Decoupling
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Layer Stack
      2. 12.1.2 Routing High-Speed Differential Signal Traces (RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+)
      3. 12.1.3 DVI Connector
    2. 12.2 Layout Example
    3. 12.3 TI PowerPAD 100-TQFP Package
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

TI PowerPAD 100-TQFP Package

The TFP401/401A is packaged in TI's thermally enhanced PowerPAD 100-TQFP packaging. The PowerPAD package is a 14-mm × 14-mm × 1-mm TQFP outline with 0.5-mm lead pitch. The PowerPAD package has a specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline. The TI 100-TQFP PowerPAD package offers a back-side solder plane that connects directly to the die mount pad for enhanced thermal conduction. Soldering the back side of the TFP401/401A to the application board is not required thermally, because the device power dissipation is well within the package capability when not soldered. However, to minimize stress on peripheral pins, it is highly recommended to solder the thermal pad to PCB.

Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations. Because the die pad is electrically connected to the chip substrate and hence to chip ground, connection of the PowerPAD's back side to a PCB ground plane helps to improve EMI, ground bounce, and power-supply noise performance. To minimize stress on peripheral pins, however, it is highly recommended to solder the thermal pad to PCB.

Table 12-1 outlines the thermal properties of the TI 100-TQFP PowerPAD package. The 100-TQFP non-PowerPAD package is included only for reference.

Table 12-1 TI 100-TQFP (14 mm × 14 mm × 1 mm) / 0.5-mm Lead Pitch
PARAMETER WITHOUT
PowerPAD™ Package
PowerPAD™ Package,
NOT CONNECTED TO PCB
THERMAL PLANE
PowerPAD™ Package,
CONNECTED TO PCB
THERMAL PLANE(1)
Theta-JA(1)(2) 45°C/W 27.3°C/W 17.3°C/W
Theta-JC(1)(2) 3.11°C/W 0.12°C/W 0.12°C/W
Maximum power dissipation(1)(2)(3) 1.6 W 2.7 W 4.3 W
Specified with 2-oz. (0.071 mm thick) Cu PCB plating
Airflow is at 0 LFM (0 m/s) (no airflow)
Measured at ambient temperature, TA = 70°C