JAJSOC1H March   2000  – March 2022 TFP401 , TFP401A

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Digital I/O Electrical Characteristics
    6. 7.6 DC Electrical Characteristics
    7. 7.7 AC Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TMDS Pixel Data and Control Signal Encoding
      2. 9.3.2 TFP401/401A Clocking and Data Synchronization
      3. 9.3.3 TFP401/401A TMDS Input Levels and Input Impedance Matching
      4. 9.3.4 TFP401A Incorporates HSYNC Jitter Immunity
    4. 9.4 Device Functional Modes
      1. 9.4.1 TFP401/401A Modes of Operation
      2. 9.4.2 TFP401/401A Output Driver Configurations
        1. 9.4.2.1 Output Driver Power Down
        2. 9.4.2.2 Drive Strength
        3. 9.4.2.3 Time-Staggered Pixel Output
        4. 9.4.2.4 Power Management
        5. 9.4.2.5 Sync Detect
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data and Control Signals
        2. 10.2.2.2 Configuration Options
        3. 10.2.2.3 Power Supplies Decoupling
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Layer Stack
      2. 12.1.2 Routing High-Speed Differential Signal Traces (RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+)
      3. 12.1.3 DVI Connector
    2. 12.2 Layout Example
    3. 12.3 TI PowerPAD 100-TQFP Package
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1 TMDS Pixel Data and Control Signal Encoding

TMDS stands for transition-minimized differential signaling. Only one of two possible TMDS characters for a given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent, and transmits the character that minimizes the number of transitions to approximate a dc balance of the transmission line.

Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user-defined control signals CTL[3:1]. These control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. Table 9-1 maps the received input data to the appropriate TMDS input channel in a DVI-compliant system.

Table 9-1 TMDS Pixel Data and Control Signal Encoding
RECEIVED PIXEL DATA
ACTIVE DISPLAY DE = HIGH		INPUT CHANNELOUTPUT PINS
(VALID FOR DE = HIGH)
Red[7:0]Channel-2 (Rx2 ±)QE[23:16] QO[23:16]
Green[7:0]Channel-1 (Rx1 ±)QE[15:8] QO[15:8]
Blue[7:0]Channel-0 (Rx0 ±)QE[7:0] QO[7:0]
RECEIVED CONTROL DATA
BLANKING DE = LOW		INPUT CHANNELOUTPUT PINS
(VALID FOR DE = LOW)
CTL[3:2]Channel-2 (Rx2 ±)CTL[3:2]
CTL[1: 0] (1)Channel-1 (Rx1 ±)CTL1
HSYNC, VSYNCChannel-0 (Rx0 ±)HSYNC, VSYNC
(1) Some TMDS transmitters transmit a CTL0 signal. The TFP401/401A decodes and transfers CTL[3:1] and ignores CTL0 characters. CTL0 is not available as a TFP401/401A output.

The TFP401/401A discriminates between valid pixel TMDS characters and control TMDS characters to determine the state of active display versus blanking (for example, the state of DE).