JAJSOC1H March   2000  – March 2022 TFP401 , TFP401A

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Digital I/O Electrical Characteristics
    6. 7.6 DC Electrical Characteristics
    7. 7.7 AC Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TMDS Pixel Data and Control Signal Encoding
      2. 9.3.2 TFP401/401A Clocking and Data Synchronization
      3. 9.3.3 TFP401/401A TMDS Input Levels and Input Impedance Matching
      4. 9.3.4 TFP401A Incorporates HSYNC Jitter Immunity
    4. 9.4 Device Functional Modes
      1. 9.4.1 TFP401/401A Modes of Operation
      2. 9.4.2 TFP401/401A Output Driver Configurations
        1. 9.4.2.1 Output Driver Power Down
        2. 9.4.2.2 Drive Strength
        3. 9.4.2.3 Time-Staggered Pixel Output
        4. 9.4.2.4 Power Management
        5. 9.4.2.5 Sync Detect
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data and Control Signals
        2. 10.2.2.2 Configuration Options
        3. 10.2.2.3 Power Supplies Decoupling
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Layer Stack
      2. 12.1.2 Routing High-Speed Differential Signal Traces (RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+)
      3. 12.1.3 DVI Connector
    2. 12.2 Layout Example
    3. 12.3 TI PowerPAD 100-TQFP Package
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-FEE6D98B-3DE3-44E1-9D62-D29312A34AC7-low.gifFigure 6-1 PZP Package, 100-Pin HTQFP (Top View)
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 79, 83, 87, 89, 92 GND Analog ground – Ground reference and current return for analog circuitry
AVDD 82, 84, 88, 95 VDD Analog VDD – Power supply for analog circuitry. Nominally 3.3 V
CTL[3:1] 42, 41, 40 DO General-purpose control signals – Used for user-defined control. CTL1 is not powered down via PDO.
DE 46 DO Output data enable – Used to indicate time of active video display versus non-active display or blank time. During blank, only HSYNC, VSYNC, and CTL[3:1] are transmitted. During times of active display, or non-blank, only pixel data, QE[23:0], and QO[23:0] are transmitted.
High: Active display time
Low: Blank time
DFO 1 DI Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support, the ODCK clock runs continuously. For DSTN support, ODCK only clocks when DE is high; otherwise, ODCK is held low when DE is low.
High: DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.
DGND 5, 39, 68 GND Digital ground – Ground reference and current return for digital core
DVDD 6, 38, 67 VDD Digital VDD – Power supply for digital core. Nominally 3.3 V
EXT_RES 96 AI Internal impedance matching – The TFP401/401A is internally optimized for impedance matching at 50 Ω. An external resistor tied to this pin has no effect on device performance.
HSYNC 48 DO Horizontal sync output
RSVD 99 DI Reserved. Must be tied high for normal operation
OVDD 18, 29, 43, 57, 78 VDD Output driver VDD – Power supply for output drivers. Nominally 3.3 V
ODCK 44 DO Output data clock – Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode), along with DE, HSYNC, VSYNC and CTL[3:1], are synchronized to this clock.
OGND 19, 28, 45, 58, 76 GND Output driver ground – Ground reference and current return for digital output drivers
OCK_INV 100 DI ODCK polarity – Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL[3:1]) are latched.
Normal mode:
High: Latches output data on rising ODCK edge
Low: Latches output data on falling ODCK edge
PD 2 DI Power down – An active-low signal that controls the TFP401/401A power-down state. During power down, all output buffers are switched to a high-impedance state. All analog circuits are powered down and all inputs are disabled, except for PD.
If PD is left unconnected, an internal pullup defaults the TFP401/401A to normal operation.
High : Normal operation
Low: Power down
PDO 9 DI Output drive power down – An active-low signal that controls the power-down state of the output drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance state. When PDO is left unconnected, an internal pullup defaults the TFP401/401A to normal operation.
High: Normal operation/output drivers on
Low: Output drive power down
PGND 98 GND PLL GND – Ground reference and current return for internal PLL
PIXS 4 DI Pixel select – Selects between one- and two-pixels-per-clock output modes. During the 2-pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel).
High: 2-pixel/clock
Low: 1-pixel/clock
PVDD 97 VDD PLL VDD – Power supply for internal PLL
QE[8:15] 20–27 DO Even green-pixel output – Output for even and odd green pixels when in 1-pixel/clock mode. Output for even-only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE8/pin 20
MSB: QE15/pin 27
QE[16:23] 30–37 DO Even red-pixel output – Output for even and odd red pixels when in 1-pixel/clock mode. Output for even-only red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE16/pin 30
MSB: QE23/pin 37
QO[0:7] 49–56 DO Odd blue-pixel output – Output for odd-only blue pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO0/pin 49
MSB: QO7/pin 56
QO[8:15] 59–66 DO Odd green-pixel output – Output for odd-only green pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO8/pin 59
MSB: QO15/pin 66
QO[16:23] 69–75, 77 DO Odd red-pixel output – Output for odd-only red pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO16/pin 69
MSB: QO23/pin 77
QE[0:7] 10–17 DO Even blue-pixel output – Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even-only blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE0/pin 10
MSB: QE7/pin 17
RxC+ 93 AI Clock positive receiver input – Positive side of reference clock. TMDS low-voltage signal differential input pair
RxC– 94 AI Clock negative receiver input – Negative side of reference clock. TMDS low-voltage signal differential input pair
Rx0+ 90 AI Channel-0 positive receiver input – Positive side of channel-0. TMDS low-voltage signal differential input pair.
Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.
Rx0– 91 AI Channel-0 negative receiver input – Negative side of channel-0. TMDS low-voltage signal differential input pair
Rx1+ 85 AI Channel-1 positive receiver input – Positive side of channel-1 TMDS low-voltage signal differential input pair
Channel-1 receives green-pixel data in active display and CTL1 control signals in blank.
Rx1– 86 AI Channel-1 negative receiver input – Negative side of channel-1 TMDS low-voltage signal differential input pair
Rx2+ 80 AI Channel-2 positive receiver input – Positive side of channel-2 TMDS low-voltage signal differential input pair
Channel-2 receives red-pixel data in active display and CTL2, CTL3 control signals in blank.
Rx2– 81 AI Channel-2 negative receiver input – Negative side of channel-2 TMDS low-voltage signal differential input pair
SCDT 8 DO Sync detect - Output to signal when the link is active or inactive. The link is considered to be active when DE is actively switching. The TFP401/401A monitors the state of DE to determine link activity. SCDT can be tied externally to PDO to power down the output drivers when the link is inactive.
High: Active link
Low: Inactive link
ST 3 DI Output drive strength select – Selects output drive strength for high- or low-current drive. (See dc specifications for IOH and IOL vs ST state).
High: High drive strength
Low: Low drive strength
STAG 7 DI Staggered pixel select – An active-low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time-staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously.
High: Normal simultaneous even/odd pixel output
Low: Time-staggered even/odd pixel output
VSYNC 47 DO Vertical sync output
Thermal Pad — Thermal pad. Recommend soldering the package thermal pad to thermal pad on PCB. Soldering the thermal pad will help to release stress through the solder, otherwise the stress will be absorbed by the peripheral pins.
(1) DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output