JAJSOC1H
March 2000 – March 2022
TFP401
,
TFP401A
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
概要 (続き)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings (1)
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
DC Digital I/O Electrical Characteristics
7.6
DC Electrical Characteristics
7.7
AC Electrical Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
TMDS Pixel Data and Control Signal Encoding
9.3.2
TFP401/401A Clocking and Data Synchronization
9.3.3
TFP401/401A TMDS Input Levels and Input Impedance Matching
9.3.4
TFP401A Incorporates HSYNC Jitter Immunity
9.4
Device Functional Modes
9.4.1
TFP401/401A Modes of Operation
9.4.2
TFP401/401A Output Driver Configurations
9.4.2.1
Output Driver Power Down
9.4.2.2
Drive Strength
9.4.2.3
Time-Staggered Pixel Output
9.4.2.4
Power Management
9.4.2.5
Sync Detect
10
Applications and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Data and Control Signals
10.2.2.2
Configuration Options
10.2.2.3
Power Supplies Decoupling
10.2.3
Application Curve
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.1.1
Layer Stack
12.1.2
Routing High-Speed Differential Signal Traces (RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+)
12.1.3
DVI Connector
12.2
Layout Example
12.3
TI PowerPAD 100-TQFP Package
13
Device and Documentation Support
13.1
Receiving Notification of Documentation Updates
13.2
サポート・リソース
13.3
Trademarks
13.4
Electrostatic Discharge Caution
13.5
Glossary
14
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PZP|100
MPQF053D
サーマルパッド・メカニカル・データ
PZP|100
PPTD033I
発注情報
jajsoc1h_oa
jajsoc1h_pm
8
Parameter Measurement Information
Figure 8-1
Rise and Fall Times of Data and Control Signals
Figure 8-2
Rise and Fall Times of ODCK
Figure 8-3
ODCK Frequency
Figure 8-4
Data Setup and Hold Times to Rising and Falling Edges of ODCK
Figure 8-5
ODCK High to QE[23:0] Staggered Data Output
Figure 8-7
Delay From
PD
Low to Hi-Z Outputs
Figure 8-9
Delay From
PD
Low to High Before Inputs Are Active
Figure 8-6
Analog Input Intra-Pair Differential Skew
Figure 8-8
Delay From
PDO
Low to Hi-Z Outputs
Figure 8-10
Minimum Time
PD
Low
Figure 8-11
Analog Input Channel-to-Channel Skew
Figure 8-12
Time Between DE Transitions to SCDT Low and SCDT High
Figure 8-13
Minimum DE Low and Maximum DE High