JAJSFG7L June   1999  – July 2024 THS4031 , THS4032

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - THS4031
    5. 5.5 Thermal Information - THS4032
    6. 5.6 Electrical Characteristics - RL = 150Ω
    7. 5.7 Electrical Characteristics - RL = 1kΩ
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-Pass Filter Configurations
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Multiplexer Selection
        2. 7.2.2.2 Signal Source
        3. 7.2.2.3 Driving Amplifier
          1. 7.2.2.3.1 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Integrated Circuit Package Design Considerations
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 商標
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • D|8
  • DGN|8
サーマルパッド・メカニカル・データ
発注情報

General PowerPAD™ Integrated Circuit Package Design Considerations

The THS403x are available in a thermally-enhanced DGN package, which is a member of the PowerPAD™ integrated circuit package family. This package is constructed using a downset lead frame upon which the die is mounted [see Figure 7-9(a) and Figure 7-9(b)]. This arrangement results in the lead frame exposed as a thermal pad on the underside of the package [see Figure 7-9(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad.

The PowerPAD integrated circuit package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are soldered), the thermal pad can be soldered to a copper area under the package. By using thermal paths within this copper area, heat is conducted away from the package into a ground plane or other heat-dissipating device.

The PowerPAD integrated circuit package represents a breakthrough in combining the small area and ease of assembly of surface mount with the more-recent, awkward mechanical methods of sinking heat.

THS4031 THS4032 Views of
                    Thermally-Enhanced DGN Package
Note: The thermal pad is electrically isolated from all pins in the package.
Figure 7-9 Views of Thermally-Enhanced DGN Package

Although there are many ways to properly dissipate heat from this device, the following steps show the recommended approach.

THS4031 THS4032 PowerPAD™
                    PCB Etch and Via Pattern Figure 7-10 PowerPAD™ PCB Etch and Via Pattern
  1. Prepare the PCB with a top-side etch pattern as shown in Figure 7-10. There must be etch for the leads as well as etch for the thermal pad.
  2. Place five holes in the area of the thermal pad. These holes must be 13 mils (0.3302mm) in diameter. The reason to keep the holes small is to discourage solder wicking through the holes during reflow.
  3. Additional vias can be placed anywhere along the thermal plane outside of the thermal pad area. This action helps dissipate the heat generated by the THS403x device. The additional vias can be of any diameter because wicking is not a concern outside of the thermal pad area.
  4. Connect all holes to the internal ground plane.
  5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS403x package must connect to the internal ground plane with a complete connection around the entire circumference of the plated-through hole.
  6. The top-side solder mask must leave the pins of the package and the thermal pad area with the five holes exposed. The bottom-side solder mask must cover the five holes of the thermal pad area, which prevents solder from pulling away from the thermal pad area during the reflow process.
  7. Apply solder paste to the exposed thermal pad area and to all the device pins.
  8. With these preparatory steps in place, the THS403x device is placed in position and run through the solder reflow operation as any standard surface-mount component.