JAJSFG7L June   1999  – July 2024 THS4031 , THS4032

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - THS4031
    5. 5.5 Thermal Information - THS4032
    6. 5.6 Electrical Characteristics - RL = 150Ω
    7. 5.7 Electrical Characteristics - RL = 1kΩ
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Offset Nulling
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving a Capacitive Load
      2. 7.1.2 Low-Pass Filter Configurations
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Multiplexer Selection
        2. 7.2.2.2 Signal Source
        3. 7.2.2.3 Driving Amplifier
          1. 7.2.2.3.1 Driving Amplifier Bandwidth Restriction
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 General PowerPAD™ Integrated Circuit Package Design Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 商標
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DGN|8
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 THS4031: D Package, 8-Pin SOIC, or DGN Package, 8-pin HVSSOP (Top View)
Table 4-1 Pin Functions: THS4031
PIN TYPE DESCRIPTION
NAME NO.
IN– 2 Input Inverting input
IN+ 3 Input Noninverting input
NC 5 — No connection
NULL 1, 8 Input Voltage offset adjust
OUT 6 Output Output of amplifier
VCC– 4 — Negative power supply
VCC+ 7 — Positive power supply
Thermal Pad Pad — Thermal pad. DGN (HVSSOP) package only. For the best thermal performance, connect this pad to a large copper plane. The thermal pad can be connected to any pin on the device, or any other potential on the board, as long as the voltage on the thermal pad remains between VCC+ and VCC–.
Figure 4-2 THS4032: D Package, 8-Pin SOIC, or DGN Package, 8-pin HVSSOP (Top View)
Table 4-2 Pin Functions: THS4032
PIN TYPE DESCRIPTION
NAME NO.
1IN– 2 Input Channel 1 inverting input
1IN+ 3 Input Channel 1 noninverting input
1OUT 1 Output Channel 1 output
2IN– 6 Input Channel 2 inverting input
2IN+ 5 Input Channel 2 noninverting input
2OUT 7 Output Channel 2 output
VCC– 4 — Negative power supply
VCC+ 8 — Positive power supply
Thermal Pad Pad — Thermal pad. DGN (HVSSOP) package only. For the best thermal performance, connect this pad to a large copper plane. The thermal pad can be connected to any pin on the device, or any other potential on the board, as long as the voltage on the thermal pad remains between VCC+ and VCC–.