SLOS930B November 2015 – November 2019 THS4541-Q1
PRODUCTION DATA.
Common-mode in to differential out, gain of 2 simulation | ||
Vocm input either driven to midsupply by low impedance source, or allowed to float and default to midsupply |
Single-ended to differential gain of 2 (see Figure 61), PSRR for negative supply to differential output (1-kHz simulation) |
3 lots, total of 2962 units trimmed at 5-V supply |
5-V and 3-V delta from 25°C VIO, 25 units |
–40°C to +125°C endpoint drift, 3 lots, total of 68 units |
Maximum differential output swing, Vocm at midsupply |
Vocm input floating, 3 lots, total of 2962 units |
10 MHz, 1-Vpp input single to differential gain of 2, see Figure 63 |
Single-ended input to differential output, simulated differential output impedance, (closed-loop) gain of 2 and 5, see Figure 61 |
Single-ended input to differential output, gain of 2 (see Figure 61), simulated with 1% resistor, worst-case mismatch |
Single-ended to differential, gain of 2 (see Figure 61) PSRR simulated to differential output |
Average Vocm output offset of 37 units,
Standard deviation < 2.5 mV, see Figure 63 |
Single-ended to differential gain of 2 (see Figure 61), PSRR for positive supply to differential output (1-kHz simulation) |
3 lots, total of 2962 units |
5-V and 3-V over temperature IOS, 25 units |
–40°C to +125°C endpoint drift, 3 lots, total of 68 units |
Input driven midsupply, 3 lots, total of 2962 units |
10 MHz, 1-VPP input single to differential gain of 2, see Figure 63 | ||