JAJSIB3D August   2017  – February 2021 THS4561

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V
    6. 7.6 Typical Characteristics: (VS+) – (VS–) = 12 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down Mode
      2. 9.4.2 Single-Ended Source to Differential Output Mode
        1. 9.4.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 9.4.2.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      3. 9.4.3 Differential Input to a Differential Output Mode
        1. 9.4.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Differential Open-Loop Gain and Output Impedance
      2. 10.1.2 Setting Resistor Values Versus Gain
      3. 10.1.3 Noise Analysis
      4. 10.1.4 Factors Influencing Harmonic Distortion
      5. 10.1.5 Input Overdrive Performance
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V

at TA ≈ 25°C, VOCM(1) = midsupply, differential output (VO) = VOUT+ – VOUT– = 2 VPP, RF = 1.5 kΩ, RL = 1 kΩ, 50-Ω input match, differential closed-loop gain (G) = 1 V/V, single-ended input (SE-in), differential output (diff-out), and input and output referenced to midsupply for AC-coupled tests (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VS = 5 V, VO = 200 mVPP, 2-dB peaking 60 MHz
VS = 5 V, VO = 200 mVPP G = 2 V/V 45
G = 5 V/V 12.5
G = 10 V/V 6.3
GBWP Gain-bandwidth product VO = 200 mVPP, G = 20 V/V, RF = 10 kΩ 68 MHz
LSBW Large-signal bandwidth VO = 4 VPP 20 MHz
Bandwidth for 0.1-dB flatness 5 MHz
SR Slew rate (20% – 80%) VS = 5 V, VO = 2-V step Rising 325 V/µs
Falling 230 V/µs
Overshoot and undershoot VO = 2-V step,
input tr = 10 ns		 VS = 12 V 5%
VS = 5 V 11%
0.1% settling time VO = 2-V step, input tr = 10 ns 40 ns
0.01% settling time VO = 2-V step, input tr = 10 ns 90 ns
Rise and fall time (10% – 90%) VO = 100-mV step, input tr = 2 ns 5.7 ns
HD2 Second-order harmonic distortion VS = 5 V, f = 100 kHz Vo = 2 VPP –117 dBc
Vo = 8 VPP –110
HD3 Third-order harmonic distortion VS = 5 V, f = 100 kHz Vo = 2 VPP –124
Vo = 8 VPP –106
en Input differential voltage noise f ≥ 500 Hz 4 nV/√Hz
1/f corner 8 Hz
in Input current noise, each input f ≥ 50 kHz 0.35 pA/√Hz
Overdrive recovery time VS = 5 V, G = 2 V/V,
2x output overdrive, dc-coupled		 210 ns
ZOUT Closed-loop output impedance f = 100 kHz (differential) 0.06 Ω
DC PERFORMANCE
AOL Open-loop voltage gain Vo = ±2 V 104 115 dB
VOS Input offset voltage TA = 25°C –250 ±50 250 µV
Input offset voltage drift TA = 0°C to 85°C,
TA = –40°C to 125°C		 –4 ±0.5 4 µV/°C
IB+, IB– Input bias current(3) TA = 25°C 370 600 nA
Input bias current drift TA = –40°C to 125°C 4.1 8 nA/°C
IOS Input offset current(4) TA = 25°C –20 ±2 20 nA
Input offset current drift TA = –40°C to 125°C –200 ±40 200 pA/°C
INPUT
VICML Common-mode input low TA = –40°C to 125°C, 3-dB AOL degradation from midsupply VOCM AOL VS– – 0.1 VS– V
VICMH Common-mode input high 3-dB AOL degradation from midsupply
VOCM AOL 		TA = 25°C VS+ – 1.2 VS+ – 1.1 V
TA = –40°C to 125°C VS+ – 1.35 VS+ – 1.2
CMRR Common-mode rejection ratio Midsupply inputs 95 110 dB
Midsupply inputs, TA = –40°C to 125°C 108
Differential input impedance Inputs at midsupply 150 || 2.4 kΩ || pF
OUTPUT
Output voltage range low VS = 5 V VS– + 0.13 VS– + 0.25 V
VS = 5 V, TA = –40°C to 125°C VS– + 0.15 VS– + 0.3
VS = 5 V, RL = 10 kΩ VS– + 0.07
VS = 12 V VS– + 0.26 VS– + 0.4
Output voltage range high VS = 5 V VS+ – 0.25 VS+ – 0.16 V
VS = 5 V, TA = –40°C to 125°C VS+ – 0.3 VS+ – 0.18
VS = 5 V, RL = 10 kΩ VS+ – 0.09
VS = 12 V VS+ – 0.35 VS+ – 0.2
Continuous output current VO = ±3.6 V, VOCM offset < 15 mV ±27 ±31 mA
TA = –40°C to +125°C, VO = ±2.25 V,
VOCM offset < 15 mV		 ±17
Linear output current VS = 5 V, VO = ±2.7 V,, AOL > 80 dB ±20 ±22 mA
VS = 12 V, VO = ±4.6 V, AOL > 80 dB ±22 ±27
VS = 12 V, TA = –40°C to +125°C,
VO = ±3.1 V, AOL > 80 dB		 ±15
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(1)
Small-signal bandwidth VOCM = 10 mVPP 22 MHz
Large-signal bandwidth VOCM = 1 VPP 1.9 MHz
Slew rate(2) (20% – 80%) VOCM = 0.5-V step 4 V/µs
DC output balance VOCM fixed midsupply,
VOCM/VO (VO = ±1 V)		 86 dB
Output balance VOCM fixed midsupply,
VOCM/VO (–3-dB from dc)		 800 Hz
Gain VOCM = 0 V 0.997 1 1.003 V/V
Input bias current –0.5 –0.1 0.5 µA
+PSR to VOCM VOCM = midsupply 72 78 dB
–PSR to VOCM VOCM = midsupply 70 76 dB
Input impedance 200 || 1.5 kΩ || pF
Default VOCM offset Relative to midsupply, VOCM pin floating –40 8 40 mV
Default VOCM offset voltage drift TA = –40℃ to 125℃ 120 200 600 µV/℃
VOCM offset voltage VOCM driven to midsupply –3.5 0.25 3.5 mV
VOCM offset voltage drift TA = –40°C to 125°C –15 3 15 µV/°C
VOCM range low TA = 25°C, < ±4-mV shift from
midsupply offset		 VS– + 0.45 VS– + 0.5 V
TA = –40°C to 125°C, < ±4-mV shift
from midsupply offset		 VS– + 0.6
VOCM range high TA = 25°C, < ±4-mV shift from
midsupply offset		 VS+ – 1.2 VS+ – 1.1 V
TA = –40°C to 125°C, < ±5-mV shift
from midsupply offset		 VS+ – 1.3
POWER SUPPLY
Specified operating voltage 2.85 12.6 V
IQ Quiescent current VS = 2.85 V, no load, TA = 25°C 710 760 810 µA
VS = 5 V, no load, TA = 25°C 725 775 825
VS = 5 V, no load,
TA = –40°C to 125°C		 700 900
VS = 12 V, no load, TA = 25°C 770 825 880
VS = 12 V, no load,
TA = –40°C to 125°C		 740 1000
Quiescent current drift No load, TA = –40°C to 125°C 0.7 1.3 µA/°C
PSRR Power-supply rejection ratio Either supply to input VOS 92 110 dB
POWER DOWN
VEN Enable voltage threshold PD = VEN, guaranteed on above VS+ – 1.2 VS+ – 0.5 V
VDIS Disable voltage threshold PD = VDIS, guaranteed off below VS+ – 1.7 VS+ – 1.8 V
PD pin bias current PD = VS+ – 0.5 V (amplifier enabled) 1.2 3.5 µA
PD pin bias current PD = VS– (amplifier disabled) –3 –1.9 µA
Peak PD pull-down bias current Switch amplifier on to off 175 µA
Power-down quiescent current No load 3 15 40 µA
Turnon time delay Time from PD = high to VO = 90%
of final value		 600 ns
Turnoff time delay Time from PD = low to VO = 10%
of original value		 1.5 µs
(1) VOCM refers to the voltage at VOCM pin. VOCM = [(VOUT+ + VOUT–)/2] refers to the average output voltage.
(2) Average of the rising and falling slew rate.
(3) Current out of the node is considered positive.
(4) IOS = IB+ – IB–.