JAJSC60F April   2016  – June 2024 THS6212

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12 V
    6. 5.6 Electrical Characteristics VS = 28 V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics: VS = 12 V
    9. 5.9 Typical Characteristics: VS = 28 V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage and Current Drive
      2. 6.3.2 Driving Capacitive Loads
      3. 6.3.3 Distortion Performance
      4. 6.3.4 Differential Noise Performance
      5. 6.3.5 DC Accuracy and Offset Control
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Wideband Current-Feedback Operation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Dual-Supply Downstream Driver
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Line Driver Headroom Requirements
          2. 7.2.2.2.2 Computing Total Driver Power for Line-Driving Applications
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHF|24
サーマルパッド・メカニカル・データ
発注情報
7.2.2.2.1 Line Driver Headroom Requirements

The first step in a transformer-coupled, twisted-pair driver design is to compute the peak-to-peak output voltage from the target specifications. This calculation is done using Equation 8 to Equation 11:

Equation 8. THS6212

where

  • PL = power at the load
  • VRMS = voltage at the load
  • RL = load impedance

These values produce the following:

Equation 9. THS6212
Equation 10. THS6212

where

  • VP = peak voltage at the load
  • CF = crest factor
Equation 11. THS6212

where

  • VLPP = peak-to-peak voltage at the load

Consolidating Equation 8 to Equation 11 allows the required peak-to-peak voltage at the load to be expressed as a function of the crest factor, the load impedance, and the power at the load, as given by Equation 12:

Equation 12. THS6212

VLPP is usually computed for a nominal line impedance and can be taken as a fixed design target.

The next step in the design is to compute the individual amplifier output voltage and currents as a function of peak-to-peak voltage on the line and transformer-turns ratio.

When this turns ratio changes, the minimum allowed supply voltage also changes. The peak current in the amplifier output is given by Equation 13:

Equation 13. THS6212

where

THS6212 Driver Peak Output VoltageFigure 7-5 Driver Peak Output Voltage

With the previous information available, a supply voltage and the turns ratio desired for the transformer can now be selected, and the headroom for the THS6212 can be calculated.

The model shown in Figure 7-6 can be described with Equation 14 and Equation 15 as:

  1. The available output swing:
    Equation 14. THS6212
  2. Or as the required supply voltage:
    Equation 15. THS6212

The minimum supply voltage for power and load requirements is given by Equation 15.

V1, V2, R1, and R2 are given in Table 7-1 for the ±14-V operation.

THS6212 Line Driver Headroom ModelFigure 7-6 Line Driver Headroom Model
Table 7-1 Line Driver Headroom Model Values
VSV1R1V2R2
±14 V1 V0.6 Ω1 V1.2 Ω

When using a synthetic output impedance circuit (see Figure 7-4), a significant drop in bandwidth occurs from the specification provided in the Electrical Characteristics tables. This apparent drop in bandwidth for the differential signal is a result of the apparent increase in the feedback transimpedance for each amplifier. This feedback transimpedance equation is given by Equation 16:

Equation 16. THS6212

To increase the 0.1-dB flatness to the frequency of interest, adding a serial RC in parallel with the gain resistor can be needed, as shown in Figure 7-7.

THS6212 0.1-dB Flatness Compensation CircuitFigure 7-7 0.1-dB Flatness Compensation Circuit