SBOS643A April   2014  – May 2014 THS6226A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = +12 V
    6. 6.6 Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High Output Current Line Driver
      2. 7.3.2 Charge Pump
      3. 7.3.3 Voltage Reference
      4. 7.3.4 Logic
      5. 7.3.5 Active Impedance
      6. 7.3.6 RESET Pin
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming the Device
      2. 7.5.2 Quiescent Current
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • Digitally-Adjustable Quiescent Current:
    9.4 mA to 24.8 mA
  • Bias Current Step: 1.0 mA
  • Independent Voltage Boost and Main Line Driver Disable
  • Low-Power Line Termination Mode
  • Full Capacitor Recharge: 200 µs
  • Low Input Voltage Noise Density:
    6.5 nV/√Hz Input-Referred Voltage Noise
  • Low MTPR Distortion:
    70 dB with +19.8 dBm G.993.2—Profile 8b
  • –83-dBc HD3 (1 MHz, 60-Ω Differential)
  • High Output Current: 383 mA into 60 Ω
  • Wide Output Swing: 40 VPP (+12-V, 60-Ω Differential Load with a 1:1.4 Transformer)
  • Wide Bandwidth: 97 MHz
  • Port-to-Port Separation: 90 dB at 1 MHz
  • PSRR: 70 dB at 1 MHz for Good Isolation

2 Applications

  • Ideal for All VDSL2 Profiles
  • Backwards-Compatible with ADSL, ADSL2+, and ADSL2++ Systems

3 Description

The THS6226A is a dual-port, class H, current-feedback architecture, differential line driver amplifier system ideal for xDSL systems. The device is targeted for use in very-high-bit-rate digital subscriber line 2 (VDSL2) line driver systems that enable native DTM signals while supporting greater than 20.5-dBm line power (up to 8.5 MHz) with good linearity, supporting the G.993.2 VDSL2 8b profile. The device is also fast enough to support central-office transmissions of 14.5-dBm line power up to 30 MHz.

The unique architecture of the device allows quiescent current to be minimal while still achieving very high linearity. Differential distortion, under full bias conditions, is –91 dBc at 1 MHz and reduces to only –75 dBc at 5 MHz. Fixed multiple bias settings of the amplifiers offer enhanced power savings for line lengths where the full performance of the amplifier is not required. To allow for even more flexibility and power savings on all profiles, quiescent current is digitally adjustable from 7.6 mA to 23 mA with a bias current step of 1.0 mA. For systems where additional power savings while not transmitting are desired, the device can be used in its line termination mode to maintain impedance matching.

The wide output swing on 12-V power supplies, coupled with excellent current drive, allows for wide dynamic headroom, keeping distortion minimal. The device is available in a VQFN-32 PowerPAD™ package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
THS6226A VQFN (32) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at the end of the datasheet.

Typical VDSL2 Line Driver Circuit Using One Port of the THS6226A

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Power Consumption vs Tx

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