JAJSLB3A June 2016 – February 2021 THS6302
PRODUCTION DATA
The THS6302 programming is controlled by two pins for each channel. These pins use three-level logic to create nine different combinations for each pair of pins. The pins have a high state (1) when the pin voltage is greater than 2.3 V, a low state (0) when the pin voltage is less than 0.6 V, and an open state (Z) where the pin floats at approximately 1.4 V or can be driven between 1.2 V and 1.6 V. The pins are labeled Mxy where x is the channel number that the pin is associated with and y is the pin number. Table 7-1 shows the logic combinations for the two pins and the corresponding power modes.
| BIAS CONTROL PINS | BIAS MODE DESCRIPTION | TYPICAL QUIESCENT CURRENT | |
|---|---|---|---|
| Mx1 | Mx2 | ||
| 0 | 0 | Line termination, high power | 9.5 mA |
| Z | 0 | Line termination, low power | 6.3 mA |
| 1 | 0 | G.Fast 212 MHz | 39 mA |
| 0 | Z | ADSL2+ | 14.5 mA |
| Z | Z | Power down | 1.35 mA |
| 1 | Z | Alternate VDSL (high power) | 28.0 mA |
| 0 | 1 | Alternate G.Fast 106 MHz (low power) | 17.8 mA |
| Z | 1 | VDSL | 19.5 mA |
| 1 | 1 | G.Fast 106 MHz | 23.0 mA |