JAJSKV9B December   2020  – October 2021 THVD1400 , THVD1420

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings [IEC]
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation Characteristics
    7. 5.7  Electrical Characteristics
    8. 5.8  Switching Characteristics (THVD1400)
    9. 5.9  Switching Characteristics (THVD1420)
    10. 5.10 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Receiver Failsafe
        5. 8.2.1.5 Transient Protection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2 Layout Example

GUID-20201216-CA0I-W3KH-J4FB-LTDR0K5HZZQS-low.gifFigure 10-1 Layout Example for SOIC package
GUID-20210401-CA0I-8PXP-V5VD-SNTPQ8C4BFV8-low.pngFigure 10-2 Layout Example for Co-layout of SOIC (D) and SOT (DRL)