JAJSLR8B April   2021  – September 2021 THVD1439 , THVD1439V , THVD1449 , THVD1449V

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics (THVD1439, THVD1439V)
    9. 6.9  Switching Characteristics (THVD1449, THVD1449V)
    10. 6.10 代表的特性
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Electrostatic Discharge (ESD) Protection
      2. 8.3.2 Electrical Fast Transient (EFT) Protection
      3. 8.3.3 Surge Protection
      4. 8.3.4 Enhanced Receiver Noise Immunity
      5. 8.3.5 Failsafe Receiver
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

6.9 Switching Characteristics (THVD1449, THVD1449V)

12-Mbps devices (THVD1449, 49V), over recommended operating conditions. All typical values are at 25 ℃.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
tr, tf Differential output rise/fall time RL = 54 Ω, CL = 50 pF See Figure 7-3  2 12 25 ns
tPHL, tPLH Propagation delay 7 10 25 ns
tSK(P) Pulse skew, |tPHL – tPLH| 3.5 ns
tPHZ, tPLZ Disable time See Figure 7-4 and Figure 7-5 25 75 ns
tPZH, tPZL Enable time RE = 0 V 18 65 ns
RE = VCC 2 4 μs
tSHDN Pulse width (logic low) on DE pin to initiate device  shutdown RE = VCC 300 ns
Receiver
tr, tf Differential output rise/fall time CL = 15 pF See Figure 7-6  3 10 ns
tPHL, tPLH Propagation delay 30 60 110 ns
tSK(P) Pulse skew, |tPHL – tPLH| 4 ns
tPHZ, tPLZ Disable time 10 30 ns
tPZH(1),
tPZL(1),
tPZH(2),
tPZL(2) 		Enable time DE = VCC See Figure 7-7  90 130 ns
DE = 0 V See Figure 7-8  4 10 μs
tD(OFS) Delay to enter fail-safe operation CL = 15 pF See Figure 7-9  14 20 36 μs
tD(FSO) Delay to exit fail-safe operation 25 35 55 ns
tSHDN Pulse width (logic high) on RE pin to initiate device  shutdown DE = 0 V 300 ns