JAJSNN8A
January 2024 – August 2024
THVD2419
,
THVD2429
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
ESD Ratings - IEC Specifications
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Power Dissipation
6.7
Electrical Characteristics
6.8
Switching Characteristics 250kbps
6.9
Switching Characteristics 20Mbps
6.10
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.3
Feature Description
8.3.1
Electrostatic Discharge (ESD) Protection
8.3.2
Electrical Fast Transient (EFT) Protection
8.3.3
Surge Protection
8.3.4
Enhanced Receiver Noise Immunity
8.3.5
Failsafe Receiver
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Data Rate and Bus Length
9.2.1.2
Stub Length
9.2.1.3
Bus Loading
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Device Support
10.2
ドキュメントの更新通知を受け取る方法
10.3
サポート・リソース
10.4
Trademarks
10.5
静電気放電に関する注意事項
10.6
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DRC|10
MPDS117L
サーマルパッド・メカニカル・データ
DRC|10
QFND013N
発注情報
jajsnn8a_oa
9.4.2
Layout Example
Figure 9-7
THVD2419, THVD2429 Layout Example (SOIC Package)
Figure 9-8
THVD2419, THVD2429 Layout Example (VSON Package)